16 X 16 Bit Complex Multiplier

The PDSP16116 contains four 16316 array multipliers, two 32-bit adder/subtractors and all the control logic required to support Block Floating Point Arithmetic as used in FFT applications. The PDSP16116A variant will multiply two complex (16116) bit words every 50ns and can be configured to outpu

Complex Accumulator

The PDSP16318 contains two independent 20-bit Adder/Subtractors combined with accumulator registers and shift structures. The four port architecture permits full 10MHz throughout in FFT and filter applications. Two PDSP16318s combined with a single PDSP16112A Complex Multiplier provide a complete

16 by 16 Bit Complex Multiplier

The PDSP16116A will multiply two complex (16 + 16) bit words every 50ns and can be configured to output the complete complex (32 + 32) bit result within a single cycle. The data format is fractional twos complement. FEATURES ■ Complex Number (16 + 16) X (16 + 16) Multiplication ■ Full 32 bit Re

32K BUCKET BUFFER

The PDSP16540 Bucket Buffer is for use in systems which require a reservoir in which a block of data is accumulated, whilst previous data is being transferred to other system elements and then processed. It thus prevents the loss of incoming data whilst the previous block is being processed. Like

Pythagoras Processor

文件：98.95 Kbytes Page：7 Pages

16 X 16 Bit Complex Multiplier

Pythagoras Processor

文件：89.6 Kbytes Page：8 Pages

ALU and Barrel Shifter

文件：121.12 Kbytes Page：16 Pages

Complex Accumulator

文件：137.62 Kbytes Page：8 Pages

ALU and Barrel Shifter

文件：171.76 Kbytes Page：18 Pages

16 by 16 Bit Complex Multiplier

The PDSP16116A will multiply two complex (16 + 16) bit words every 50ns and can be configured to output the complete complex (32 + 32) bit result within a single cycle. The data format is fractional twos complement. FEATURES ■ Complex Number (16 + 16) X (16 + 16) Multiplication ■ Full 32 bit Re

16 X 16 Bit Complex Multiplier

The PDSP16116 contains four 16316 array multipliers, two 32-bit adder/subtractors and all the control logic required to support Block Floating Point Arithmetic as used in FFT applications. The PDSP16116A variant will multiply two complex (16116) bit words every 50ns and can be configured to outpu

16 X 16 Bit Complex Multiplier

The PDSP16116 contains four 16316 array multipliers, two 32-bit adder/subtractors and all the control logic required to support Block Floating Point Arithmetic as used in FFT applications. The PDSP16116A variant will multiply two complex (16116) bit words every 50ns and can be configured to outpu

16 X 16 Bit Complex Multiplier

The PDSP16116 contains four 16316 array multipliers, two 32-bit adder/subtractors and all the control logic required to support Block Floating Point Arithmetic as used in FFT applications. The PDSP16116A variant will multiply two complex (16116) bit words every 50ns and can be configured to outpu

16 by 16 Bit Complex Multiplier

The PDSP16116A will multiply two complex (16 + 16) bit words every 50ns and can be configured to output the complete complex (32 + 32) bit result within a single cycle. The data format is fractional twos complement. FEATURES ■ Complex Number (16 + 16) X (16 + 16) Multiplication ■ Full 32 bit Re

16 by 16 Bit Complex Multiplier

The PDSP16116A will multiply two complex (16 + 16) bit words every 50ns and can be configured to output the complete complex (32 + 32) bit result within a single cycle. The data format is fractional twos complement. FEATURES ■ Complex Number (16 + 16) X (16 + 16) Multiplication ■ Full 32 bit Re

16 by 16 Bit Complex Multiplier

The PDSP16116A will multiply two complex (16 + 16) bit words every 50ns and can be configured to output the complete complex (32 + 32) bit result within a single cycle. The data format is fractional twos complement. FEATURES ■ Complex Number (16 + 16) X (16 + 16) Multiplication ■ Full 32 bit Re

16 X 16 Bit Complex Multiplier

The PDSP16116 contains four 16316 array multipliers, two 32-bit adder/subtractors and all the control logic required to support Block Floating Point Arithmetic as used in FFT applications. The PDSP16116A variant will multiply two complex (16116) bit words every 50ns and can be configured to outpu

16 X 16 Bit Complex Multiplier

The PDSP16116 contains four 16316 array multipliers, two 32-bit adder/subtractors and all the control logic required to support Block Floating Point Arithmetic as used in FFT applications. The PDSP16116A variant will multiply two complex (16116) bit words every 50ns and can be configured to outpu

16 X 16 Bit Complex Multiplier

The PDSP16116 contains four 16316 array multipliers, two 32-bit adder/subtractors and all the control logic required to support Block Floating Point Arithmetic as used in FFT applications. The PDSP16116A variant will multiply two complex (16116) bit words every 50ns and can be configured to outpu

16 by 16 Bit Complex Multiplier

The PDSP16116A will multiply two complex (16 + 16) bit words every 50ns and can be configured to output the complete complex (32 + 32) bit result within a single cycle. The data format is fractional twos complement. FEATURES ■ Complex Number (16 + 16) X (16 + 16) Multiplication ■ Full 32 bit Re

16 by 16 Bit Complex Multiplier

The PDSP16116A will multiply two complex (16 + 16) bit words every 50ns and can be configured to output the complete complex (32 + 32) bit result within a single cycle. The data format is fractional twos complement. FEATURES ■ Complex Number (16 + 16) X (16 + 16) Multiplication ■ Full 32 bit Re

16 by 16 Bit Complex Multiplier

The PDSP16116A will multiply two complex (16 + 16) bit words every 50ns and can be configured to output the complete complex (32 + 32) bit result within a single cycle. The data format is fractional twos complement. FEATURES ■ Complex Number (16 + 16) X (16 + 16) Multiplication ■ Full 32 bit Re

16 X 16 Bit Complex Multiplier

The PDSP16116 contains four 16316 array multipliers, two 32-bit adder/subtractors and all the control logic required to support Block Floating Point Arithmetic as used in FFT applications. The PDSP16116A variant will multiply two complex (16116) bit words every 50ns and can be configured to outpu

25MHz ;5.0V; 16 x16 bit complex multiplier. For fast fourier transforms, digital filtering, radar and sonar processing, instrumentation, image processing

Amplifier Transistors PNP Silicon

Amplifier Transistors PNP Silicon

Switching Regulator for Chopper Type DC/DC Converter

Description HA16116FP/FPJ and HA16121FP/FPJ are dual-channel PWM switching regulator controller ICs for use in chopper-type DC/DC converters. This IC series incorporates totem pole gate drive circuits to allow direct driving of a power MOS FET. The output logic is preset for booster, step

Switching Regulator for Chopper Type DC/DC Converter

Description The HA16114P/FP/FPJ and HA16120FP/FPJ are single-channel PWM switching regulator controller ICs suitable for chopper-type DC/DC converters. Integrated totem-pole output circuits enable these ICs to drive the gate of a power MOSFET directly. The output logic of the HA16120 is designed

Switching Regulator for Chopper Type DC/DC Converter

Description HA16116FP/FPJ and HA16121FP/FPJ are dual-channel PWM switching regulator controller ICs for use in chopper-type DC/DC converters. This IC series incorporates totem pole gate drive circuits to allow direct driving of a power MOS FET. The output logic is preset for booster, step

Switching Regulator for Chopper Type DC/DC Converter

Description HA16116FP/FPJ and HA16121FP/FPJ are dual-channel PWM switching regulator controller ICs for use in chopper-type DC/DC converters. This IC series incorporates totem pole gate drive circuits to allow direct driving of a power MOS FET. The output logic is preset for booster, step