Features

Multimode, multichannel decoder software functionality

— Dolby Digital and Pro Logic

— MPEG2 5.1

— DTS

— Bass management

Digital audio post-processing capabilities

— 3D Virtual surround sound

— Lucasfilm THX5.1

— Soundfield processing

— Equalization

Digital Signal Processing Core

— 100 MIPS with a 100 MHz clock at 3.3 V +/- 5

— Object code compatible with the DSP56000 core

— Highly parallel instruction set

— Data arithmetic logic unit (ALU)

– Fully pipelined 24 x 24-bit parallel multiplier-accumulator (MAC)

– 56-bit parallel barrel shifter (fast shift and normalization; bit stream generation and parsing)

– Conditional ALU instructions

– 24-bit or 16-bit arithmetic support under software control

— Program control unit (PCU)

– Position independent code (PIC) support

– Addressing modes optimized for DSP applications (including immediate offsets)

– On-chip instruction cache controller

– On-chip memory-expandable hardware stack

– Nested hardware DO loops

– Fast auto-return interrupts

— Direct memory access (DMA)

– Six DMA channels supporting internal and external accesses

– One-, two-, and three- dimensional transfers (including circular buffering)

– End-of-block-transfer interrupts

– Triggering from interrupt lines and all peripherals

— Phase-locked loop (PLL)

– Software programmable PLL-based frequency synthesizer for the core clock

– Allows change of low-power divide factor (DF) without loss of lock

– Output clock with skew elimination

— Hardware debugging support

– On-Chip Emulation (OnCE‘) module

– Joint Action Test Group (JTAG) test access port (TAP)

– Address trace mode reflects internal program RAM accesses at the external port

On-Chip Memories

— Modified Harvard architecture allows simultaneous access to program and data memories

— 30720 x 24-bit on-chip program ROM1 (disabled in 16-bit compatibility mode)

— 6144 x 24-bit on-chip X-data ROM1

— 6144 x 24-bit on-chip Y-data ROM1

— Program RAM, instruction cache, X data RAM, and Y data RAM sizes are programmable

— 192 x 24-bit bootstrap ROM (disabled in sixteen-bit compatibility mode)

Off-Chip Memory Expansion

— Data memory expansion to 256K x 24-bit word memory for P, X, and Y memory using SRAM.

— Data memory expansion to 16M x 24-bit word memory for P, X, and Y memory using DRAM.

— External memory expansion port( twenty-four data pins for high speed external memory access

allowing for a large number of external accesses per sample)

— Chip select logic for glueless interface to SRAMs

— On-chip DRAM controller for glueless interface to DRAMs

Peripheral and Support Circuits

— Enhanced serial audio interface (ESAI) includes:

– Six serial data lines, 4 selectable as receive or transmit and 2 transmit only.

– Master or slave capability

– I2S, Sony, AC97, and other audio protocol implementations

— Serial host interface (SHI) features:

– SPI protocol with multi-master capability

– I2C protocol with single-master capability

– Ten-word receive FIFO

– Support for 8-, 16-, and 24-bit words.

— Byte-wide parallel host interface (HDI08) with DMA support

— DAX features one serial transmitter capable of supporting S/PDIF, IEC958, IEC1937, CP-340,

and AES/EBU digital audio formats; alternate configuration supports up to two GPIO lines

— Triple timer module with single external interface or GPIO line

— On-chip peripheral registers are memory mapped in data memory space

• Reduced Power Dissipation

— Very low-power (3.3 V) CMOS design

— Wait and stop low-power standby modes

— Fully-static logic, operation frequency down to 0 Hz (dc)

— Optimized power management circuitry (instruction-dependent, peripheral-dependent, and

mode-dependent)