DSP56300 Core Description

The DSP56371 uses the DSP56300 core, a high-performance, single clock cycle per instruction engine that

provides up to twice the performance of Motorola's popular DSP56000 core family while retaining code

compatibility with it.

The DSP56300 core family offers a new level of performance in speed and power, provided by its rich

instruction set and low power dissipation, thus enabling a new generation of wireless, telecommunications

and multimedia products. For a description of the DSP56300 core, see Section 2.4 DSP56300 Core

Functional Blocks. Significant architectural enhancements to the DSP56300 core family include a barrel

shifter, 24-bit addressing, an instruction patch module and direct memory access (DMA).

The DSP56300 core family members contain the DSP56300 core and additional modules. The modules

are chosen from a library of standard pre-designed elements such as memories and peripherals. New

modules may be added to the library to meet customer specifications. A standard interface between the

DSP56300 core and the on-chip memory and peripherals supports a wide variety of memory and

peripheral configurations. Refer to DSP56371 User’s Manual, Memory Configuration section.

Core features are described fully in the DSP56300 Family Manual. Pinout, memory and peripheral

features are described in this manual.

• DSP56300 modular chassis

— 181 Million Instructions Per Second (MIPS) with a 181 MHz clock at an internal logic supply

(QVDDL) of 1.25 V

— Object Code Compatible with the 56K core

— Data ALU with a 24 x 24 bit multiplier-accumulator and a 56-bit barrel shifter. 16-bit

arithmetic support

— Program Control with position independent code support and instruction patch support

— EFCOP running concurrently with the core, capable of executing 181 million filter taps per

second at peak performance

— Six-channel DMA controller

— Low jitter, PLL based clocking with a wide range of frequency multiplications (1 to 255),

predivider factors (1 to 31) and power saving clock divider (2i: i=0 to 7). Reduces clock noise.

— Internal address tracing support and OnCE for Hardware/Software debugging

— JTAG port

— Very low-power CMOS design, fully static design with operating frequencies down to DC

— STOP and WAIT low-power standby modes

• On-chip Memory Configuration

— 48Kx24 Bit Y-Data RAM and 32Kx24 Bit Y-Data ROM

— 36Kx24 Bit X-Data RAM and 32Kx24 Bit X-Data ROM

— 64Kx24 Bit Program and Bootstrap ROM

— 4Kx24 Bit Program RAM.

— PROM patching mechanism

— Up to 32Kx24 Bit from Y Data RAM and 8Kx24 Bit from X Data RAM can be switched to

Program RAM resulting in up to 44Kx24 Bit of Program RAM.

• Peripheral modules

— Enhanced Serial Audio Interface (ESAI): up to 4 receivers and up to 6 transmitters, master or

slave. I2S, left justified, right justified, Sony, AC97, network and other programmable

protocols

— Enhanced Serial Audio Interface I (ESAI_1): up to 4 receivers and up to 6 transmitters, master

or slave. I2S, left justified, right justified, Sony, AC97, network and other programmable

protocols

— Serial Host Interface (SHI): SPI and I2C protocols, multi master capability in I2C mode,

10-word receive FIFO, support for 8, 16 and 24-bit words

— Triple Timer module (TEC).

— 11 dedicated GPIO pins

— Digital Audio Transmitter (DAX): 1 serial transmitter capable of supporting the SPDIF,

IEC958, CP-340 and AES/EBU digital audio formats

— Pins of unused peripherals (except SHI) may be programmed as GPIO lines