NT5CB256M16DP-EK DDR3 256M*16 BGA96 存储器 芯片
Features
? JEDEC DDR3 Compliant
- 8n Prefetch Architecture
- Differential Clock(CK/??) and_Data Strobe(DQS/???) - Double-data rate on DQs， DQS and_DM
? Data Integrity
- Auto Self Refresh (ASR) by DRAM built-in TS - Auto Refresh and_Self Refresh Modes ? Power Saving Mode
- Partial Array Self Refresh (PASR)1 - Power Down Mode
? Signal Integrity
- Configurable DS for system compatibility
- Configurable On-Die Termination
- ZQ Calibration for DS/ODT impedance accuracy via
external ZQ pad (240 ohm ± 1%)
? Signal Synchronization
- Write Leveling via MR settings 6 - Read Leveling via MPR
? Interface and_Power Supply
- SSTL_15 for DDR3:VDD/VDDQ=1.5V(±0.075V) - SSTL_1353
for DDR3L:VDD/VDDQ=1.35V(-0.067/+0.1V)
