F81803 TQFP-64

发布企业:深圳市晨豪科技有限公司时间:2022-7-2 9:26:00

企业深圳市晨豪科技有限公司

联系人:罗先生/严小姐/叶先生/邹先生

微信:87680558

手机:13923798387

电话:0755-82732291 /0755-85274662

地址:深圳市福田区中航路新亚洲电子商城一期2A103

F81803 ,全新原装,门市自取或当天发货。
F81803

The F81803 which is the featured IO chip for PC system is equipped with ATX_AT Strapping pin, two UART Ports with up to 128 bytes FIFO, provide 9 bit (multi-drop) function, one 80 port (multi with COM2), Hardware Keyboard Controller. The UART supports legacy speeds up to 115.2K bps as well as even higher baud rates of 230K, 460K, or 921K bps to support higher speed modems. The F81803 integrates with hardware monitor, 7 sets of voltage sensor, 2 sets of creative auto-controlling fans and_2 temperature sensor pins for the accurate dual current type temperature measurement for CPU thermal diode or external transistors 2N3906. Others, the F81803 supports newest AMD TSI, Intel PECI 3.0 interfaces and_SMBus for temperature sensing and_provides the power sequence controller function for AMD platform.

The F81803 provides flexible features for multi-directional application. For instance, the F81803 provides 15 GPIO pins (multi-pin), IRQ sharing function also designed in UART feature for particular usage and_accurate current mode H/W monitor will be worth in measurement of temperature, provides 3 modes fan speed control mechanism included Manual Mode/Stage Auto Mode/Linear Auto Mode for users’ selection.

In order to save the current consumption when the system is in the soft off state which is so called power saving function. The power saving function supports that system boot-on not only by pressing the power button but also by the wake-up events via RI#. When the system enters the S4/S5 state, F81803 can cut off the VSB power rail which supplies power source to the devices like the LAN chip, the chipset, the SIO, the audio codec, DRAM, and_etc. The PC system can be simulated to G3-like state when system enters the S4/S5 states. At the G3-like state, the F81803 consumes the 5VA power rail only. The integrated two control pins are utilized to turn on or off VSB power rail in the G3-like status. The turned on VSB rail is supplied to a wake up device to fulfill a low power consumption system which supports a wake up function.

These features as above description will help you more and_improve the product value. The F81803 is powered by 3.3V voltage, with the LPC interface in the green package of 64-TQFP(7mm*7mm).

General Functions

- Comply with LPC Spec. 1.1

- Support DPM (Device Power Management), ACPI

- Support AMD power sequence controller

- Provides two UARTs with programmable 16/32/64/128 bytes FIFO

- Hardware KBC

- H/W monitor functions

- Support AMD TSI, MXM, Intel PECI 3.0 interface

- Provide SMBus slave & master_function

- Provide 2 sets of SMBus Interface.

- 15 GPIO Pins for flexible application

- Provide Power Saving Function (Comply ERP lot 6.0)

- Support Intel Deep Sleep Well (DSW) Timing Sequence

- Provide wake-up events via power button, RI#

- Provide ATX emulates AT function

- 24/48 MHz clock input

- Packaged in 64-TQFP and_powered by 3.3VCC

UART

- Two high-speed 16C550/16C650/16C750/16C850/16C950 compatible UART with programmable 16/32/64/128

bytes FIFO

- Baud rate up to 115.2K, max. up to 1.5M

- Support IRQ sharing

- Support Ring-In Wakeup

- Provide auto flow control function

- Provide Multi drop_(9-bits) Function for Gaming Machine

- Support programmable register for TX/RX only, Mondem control, & fully UART function

80-Port Interface

- Monitor 0x80 Port and_output the value via signals defined for 7-segment display.

- High nibble and_low nibble are outputted interleaved at 1KHz frequency.

- 80-Port output via COM2 interface.

- Provide MXM/PECI/TSI/T1/T2 value via 80-port

Hardware Monitor Functions

- 2 dual current type (±3℃) thermal inputs for CPU thermal diode and_2N3906 transistors

- Temperature range -40℃~127℃

- 7 sets voltage monitoring (2 external and_5 internal powers)

- Voltage monitor supports Over/Under Voltage Protection (OVP/UVP)

- High limit signal (PME#) for Vcore level

- 2 fan speed monitoring inputs

- 2 fan speed PWM/DC control outputs(support 3 wire and_4 wire fans)

- The Fan PWM output frequency can be programmed as for LCD backlight adjustment

- Stage auto mode ( 4-Limit and_5-Stage)/Linear auto mode/Manual mode

- OVT# hardware signals output

- Case open detection (assert via PME#)

- WATCHDOG comparison of all monitored values

- PSIN# detection time flag is programmable 1s(default)/2s/3s/4s (Usage: Enter BIOS setting page

under the quick booting WIN 8 OS)

Keyboard Controller

- LPC interface support serial interrupt channel 1, 12.

- Two 16bit Programmable Address fully decoder, default 0x60 and_0x64.

- Support two PS/2 interface, one for PS/2 mouse and_the other for keyboard.

- Programmable compatibility with the 8042.

- Support both interrupt and_polling modes.

- Fast Gate A20 and_Hardware Keyboard Reset.

Power Saving Controller

- ACPI Timing and_Power Control

- Wake-up Supported

- G3-like Timing Control

- Comply With ERP Lot 6.0

- Built in Soft Start Function for Two Control Pins with VSB Power Sources Control.

- Event in input via GPIo05~06, GPIO16 , GPIO44~47, RI# pins

GPIO Function

- Total 15 pins GPIO

- GPIO0X could be reset by 3VA/VBAT via the register setting

- GPIO05, GPIO06, GPIO16 support SMI event via PME# or SIRQ

- Scan Code

- All GPIO supports digit IO for Input/Output control, Output data control, input status.

- Support High/Low Level/Pulse, Open Drain/Push Pull function selection

Watch Dog Timer

- Time resolution minute/second

- Maximum 256 minutes or 256 seconds

- Output signal via WDTRST#/PWOK

- WDT could also wake up via PME#, PSOUT#

- Provide hardware strapping pin & auto reload function

Integrate Intel PECI 3.0Spec.

Integrate Intel Cougar Point Timing/DSW Timing

Support AMD Power Sequence Controller

Intel Block Read/Write SMBus Interface

Provide ATX Emulates AT Function

AMD TSI/MXM/I2C Interface

- Support slave interface to report the hardware monitor data under S0/S3/S5

- I2C slave default address is 5Ch

- Support master_interface to get the thermal data via PCH & MXM module

- Provide 2 sets of SMBus for TSI/MXM/I2C interface.

- AMD TSI/MXM/I2C interfaces could be selected individually via 2 sets of pins à pin 28 (GPIO06/TSI_SCL/I2C_SCL),

& pin 29(PECI/TSI_SDA/I2C_SDA);_pin 34 (MDATA/TSI_SDA/I2C_SDA), & pin 35 (MCLK/TSI_SCL/I2C_SCL).

Package

- 64-TQFP (7*7) Green Package

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