512Mb DDR SDRAM

Feature z Power Supply Voltage: VDD=VDDQ=2.5V±0.2V (DDR-333) VDD=VDDQ=2.6V±0.1V (DDR-400/500) z 4 internal memory banks for concurrent operation. z CAS Latency: 2, 2.5 and 3 z Double Data Rate Architecture z Bidirectional data strobe (DQS) is transmitted and received with data, to be used

512Mb DDR SDRAM

Feature z Power Supply Voltage: VDD=VDDQ=2.5V±0.2V (DDR-333) VDD=VDDQ=2.6V±0.1V (DDR-400/500) z 4 internal memory banks for concurrent operation. z CAS Latency: 2, 2.5 and 3 z Double Data Rate Architecture z Bidirectional data strobe (DQS) is transmitted and received with data, to be used

512Mb DDR SDRAM

Feature z Power Supply Voltage: VDD=VDDQ=2.5V±0.2V (DDR-333) VDD=VDDQ=2.6V±0.1V (DDR-400/500) z 4 internal memory banks for concurrent operation. z CAS Latency: 2, 2.5 and 3 z Double Data Rate Architecture z Bidirectional data strobe (DQS) is transmitted and received with data, to be used

512Mb DDR SDRAM

Feature z Power Supply Voltage: VDD=VDDQ=2.5V±0.2V (DDR-333) VDD=VDDQ=2.6V±0.1V (DDR-400/500) z 4 internal memory banks for concurrent operation. z CAS Latency: 2, 2.5 and 3 z Double Data Rate Architecture z Bidirectional data strobe (DQS) is transmitted and received with data, to be used

512Mb DDR SDRAM

Feature z Power Supply Voltage: VDD=VDDQ=2.5V±0.2V (DDR-333) VDD=VDDQ=2.6V±0.1V (DDR-400/500) z 4 internal memory banks for concurrent operation. z CAS Latency: 2, 2.5 and 3 z Double Data Rate Architecture z Bidirectional data strobe (DQS) is transmitted and received with data, to be used

512Mb DDR SDRAM

Feature z Power Supply Voltage: VDD=VDDQ=2.5V±0.2V (DDR-333) VDD=VDDQ=2.6V±0.1V (DDR-400/500) z 4 internal memory banks for concurrent operation. z CAS Latency: 2, 2.5 and 3 z Double Data Rate Architecture z Bidirectional data strobe (DQS) is transmitted and received with data, to be used

标准型DRAM-DDR

车用与工规等级DRAM-DDR