Octal D-type flip-flop with enable

DESCRIPTION The 74F377A has 8 edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered clock (CP) input loads all flip-flops simultaneously when the Enable (E) input is Low. The register is fully edge triggered. The state of each D input, one set-up time befor

Octal D-type flip-flop with enable

DESCRIPTION The 74F377A has 8 edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered clock (CP) input loads all flip-flops simultaneously when the Enable (E) input is Low. The register is fully edge triggered. The state of each D input, one set-up time befor

Octal D-type flip-flop with enable

Octal D-Type Flip-Flop with Clock Enable

General Description The 74F377 has eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) input loads all flip-flops simultaneously, when the Clock Enable (CE) is LOW. The register is fully edge-triggered. The state of each D input, one set

Octal D-type flip-flop with enable

DESCRIPTION The 74F377A has 8 edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered clock (CP) input loads all flip-flops simultaneously when the Enable (E) input is Low. The register is fully edge triggered. The state of each D input, one set-up time befor

Octal D-Type Flip-Flop with Clock Enable

General Description The 74F377 has eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) input loads all flip-flops simultaneously, when the Clock Enable (CE) is LOW. The register is fully edge-triggered. The state of each D input, one set

Octal D-Type Flip-Flop with Clock Enable

文件：75.98 Kbytes Page：7 Pages

Octal D Flip-Flop with Clock Enable

文件：143.07 Kbytes Page：8 Pages