Hex D flip-flops

DESCRIPTION The 74F174 has six edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) and Master Reset (MR) inputs load and reset (clear) all flip-flops simultaneously. The register is fully edge-triggered. The state of each D input, one setup ti

Hex D flip-flops

DESCRIPTION The 74F174 has six edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) and Master Reset (MR) inputs load and reset (clear) all flip-flops simultaneously. The register is fully edge-triggered. The state of each D input, one setup ti

Hex D flip-flops

封装/外壳：16-SOIC（0.154"，3.90mm 宽） 功能：主复位 包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：IC FF D-TYPE SNGL 6BIT 16SO 集成电路（IC） 触发器

Hex D flip-flops

封装/外壳：16-DIP（0.300"，7.62mm） 功能：主复位 包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：IC FF D-TYPE SNGL 6BIT 16DIP 集成电路（IC） 触发器

Hex D-Type Flip-Flop with Master Reset

General Description The 74F174 is a high-speed hex D-type flip-flop. The device is used primarily as a 6-bit edge-triggered storage register. The information on the D inputs is transferred to storage during the LOW-to-HIGH clock transition. The device has a Master Reset to simultaneously clear

Hex D flip-flops

DESCRIPTION The 74F174 has six edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) and Master Reset (MR) inputs load and reset (clear) all flip-flops simultaneously. The register is fully edge-triggered. The state of each D input, one setup ti

Hex D Flip-Flop with Master Reset

文件：166.34 Kbytes Page：8 Pages

Hex D-Type Flip-Flop with Master Reset

文件：79.79 Kbytes Page：7 Pages

Hex D Flip-Flop with Master Reset

文件：166.34 Kbytes Page：8 Pages