standard or self refresh

GENERAL DESCRIPTION The MT4C4001J(S) is a randomly accessed solid=state memory containing 4,194,304 bits organized in ax4 configuration.

standard or self refresh

GENERAL DESCRIPTION The MT4C4001J(S) is a randomly accessed solid=state memory containing 4,194,304 bits organized in ax4 configuration.

standard or self refresh

GENERAL DESCRIPTION The MT4C4001J(S) is a randomly accessed solid=state memory containing 4,194,304 bits organized in ax4 configuration.

standard or self refresh

GENERAL DESCRIPTION The MT4C4001J(S) is a randomly accessed solid=state memory containing 4,194,304 bits organized in ax4 configuration.

standard or self refresh

GENERAL DESCRIPTION The MT4C4001J(S) is a randomly accessed solid=state memory containing 4,194,304 bits organized in ax4 configuration.

standard or self refresh

GENERAL DESCRIPTION The MT4C4001J(S) is a randomly accessed solid=state memory containing 4,194,304 bits organized in ax4 configuration.

standard or self refresh

GENERAL DESCRIPTION The MT4C4001J(S) is a randomly accessed solid=state memory containing 4,194,304 bits organized in ax4 configuration.

standard or self refresh

GENERAL DESCRIPTION The MT4C4001J(S) is a randomly accessed solid=state memory containing 4,194,304 bits organized in ax4 configuration.

standard or self refresh

GENERAL DESCRIPTION The MT4C4001J(S) is a randomly accessed solid=state memory containing 4,194,304 bits organized in ax4 configuration.

standard or self refresh

GENERAL DESCRIPTION The MT4C4001J(S) is a randomly accessed solid=state memory containing 4,194,304 bits organized in ax4 configuration.

standard or self refresh

GENERAL DESCRIPTION The MT4C4001J(S) is a randomly accessed solid=state memory containing 4,194,304 bits organized in ax4 configuration.

1MEG x 4DRAM

standard or self refresh

GENERAL DESCRIPTION The MT4C4001J(S) is a randomly accessed solid=state memory containing 4,194,304 bits organized in ax4 configuration.

1 MEG x 4 DRAM Fast Page Mode DRAM

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