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| 型号 | 功能描述 | 生产厂家 企业 | LOGO | 操作 |
|---|---|---|---|---|
MT4C4001J | 1MEG x 4DRAM GENERAL DESCRIPTION The MT4C4001J(S) is a randomly accessed solid=state memory containing 4,194,304 bits organized in ax4 configuration. | MICRON 美光 |   | |
MT4C4001J | standard or self refresh GENERAL DESCRIPTION The MT4C4001J(S) is a randomly accessed solid=state memory containing 4,194,304 bits organized in ax4 configuration. | MICRON 美光 | | |
MT4C4001J | FAST PAGE MODE access cycle GENERAL DESCRIPTION The MT4C4001J is a randomly accessed solid-state memory containing 4,194,304 bits organized in a x4 configuration. FEATURES • Industry standard x4 pinout, timing, functions, and packages • High-performance, CMOS silicon-gate process • Single +5V±10 power supply | MICROSS | | |
MT4C4001J | 1 MEG x 4 DRAM Fast Page Mode DRAM GENERAL DESCRIPTION The MT4C4001J is a randomly accessed solid-state memory containing 4,194,304 bits organized in a x4 configuration. During READ or WRITE cycles each bit is uniquely addressed through the 20 address bits which are entered 10 bits (A0-A9) at a time. RAS is used to latch the fir | AUSTIN | | |
MT4C4001J | 1 MEG x 4 DRAM Fast Page Mode DRAM 文件：1.1819 Mbytes Page：21 Pages | AUSTIN | | |
MT4C4001J | 1MEG x 4DRAM | MICRON 美光 | | |
standard or self refresh GENERAL DESCRIPTION The MT4C4001J(S) is a randomly accessed solid=state memory containing 4,194,304 bits organized in ax4 configuration. | MICRON 美光 | | ||
standard or self refresh GENERAL DESCRIPTION The MT4C4001J(S) is a randomly accessed solid=state memory containing 4,194,304 bits organized in ax4 configuration. | MICRON 美光 | | ||
standard or self refresh GENERAL DESCRIPTION The MT4C4001J(S) is a randomly accessed solid=state memory containing 4,194,304 bits organized in ax4 configuration. | MICRON 美光 | | ||
1 MEG x 4 DRAM Fast Page Mode DRAM GENERAL DESCRIPTION The MT4C4001J is a randomly accessed solid-state memory containing 4,194,304 bits organized in a x4 configuration. During READ or WRITE cycles each bit is uniquely addressed through the 20 address bits which are entered 10 bits (A0-A9) at a time. RAS is used to latch the fir | AUSTIN | | ||
1 MEG x 4 DRAM Fast Page Mode DRAM GENERAL DESCRIPTION The MT4C4001J is a randomly accessed solid-state memory containing 4,194,304 bits organized in a x4 configuration. During READ or WRITE cycles each bit is uniquely addressed through the 20 address bits which are entered 10 bits (A0-A9) at a time. RAS is used to latch the fir | AUSTIN | | ||
1 MEG x 4 DRAM Fast Page Mode DRAM GENERAL DESCRIPTION The MT4C4001J is a randomly accessed solid-state memory containing 4,194,304 bits organized in a x4 configuration. During READ or WRITE cycles each bit is uniquely addressed through the 20 address bits which are entered 10 bits (A0-A9) at a time. RAS is used to latch the fir | AUSTIN | | ||
1 MEG x 4 DRAM Fast Page Mode DRAM GENERAL DESCRIPTION The MT4C4001J is a randomly accessed solid-state memory containing 4,194,304 bits organized in a x4 configuration. During READ or WRITE cycles each bit is uniquely addressed through the 20 address bits which are entered 10 bits (A0-A9) at a time. RAS is used to latch the fir | AUSTIN | | ||
1 MEG x 4 DRAM Fast Page Mode DRAM GENERAL DESCRIPTION The MT4C4001J is a randomly accessed solid-state memory containing 4,194,304 bits organized in a x4 configuration. During READ or WRITE cycles each bit is uniquely addressed through the 20 address bits which are entered 10 bits (A0-A9) at a time. RAS is used to latch the fir | AUSTIN | | ||
1 MEG x 4 DRAM Fast Page Mode DRAM GENERAL DESCRIPTION The MT4C4001J is a randomly accessed solid-state memory containing 4,194,304 bits organized in a x4 configuration. During READ or WRITE cycles each bit is uniquely addressed through the 20 address bits which are entered 10 bits (A0-A9) at a time. RAS is used to latch the fir | AUSTIN | | ||
1 MEG x 4 DRAM Fast Page Mode DRAM GENERAL DESCRIPTION The MT4C4001J is a randomly accessed solid-state memory containing 4,194,304 bits organized in a x4 configuration. During READ or WRITE cycles each bit is uniquely addressed through the 20 address bits which are entered 10 bits (A0-A9) at a time. RAS is used to latch the fir | AUSTIN | | ||
1 MEG x 4 DRAM Fast Page Mode DRAM GENERAL DESCRIPTION The MT4C4001J is a randomly accessed solid-state memory containing 4,194,304 bits organized in a x4 configuration. During READ or WRITE cycles each bit is uniquely addressed through the 20 address bits which are entered 10 bits (A0-A9) at a time. RAS is used to latch the fir | AUSTIN | | ||
1 MEG x 4 DRAM Fast Page Mode DRAM GENERAL DESCRIPTION The MT4C4001J is a randomly accessed solid-state memory containing 4,194,304 bits organized in a x4 configuration. During READ or WRITE cycles each bit is uniquely addressed through the 20 address bits which are entered 10 bits (A0-A9) at a time. RAS is used to latch the fir | AUSTIN | | ||
1 MEG x 4 DRAM Fast Page Mode DRAM GENERAL DESCRIPTION The MT4C4001J is a randomly accessed solid-state memory containing 4,194,304 bits organized in a x4 configuration. During READ or WRITE cycles each bit is uniquely addressed through the 20 address bits which are entered 10 bits (A0-A9) at a time. RAS is used to latch the fir | AUSTIN | | ||
1 MEG x 4 DRAM Fast Page Mode DRAM GENERAL DESCRIPTION The MT4C4001J is a randomly accessed solid-state memory containing 4,194,304 bits organized in a x4 configuration. During READ or WRITE cycles each bit is uniquely addressed through the 20 address bits which are entered 10 bits (A0-A9) at a time. RAS is used to latch the fir | AUSTIN | | ||
1 MEG x 4 DRAM Fast Page Mode DRAM GENERAL DESCRIPTION The MT4C4001J is a randomly accessed solid-state memory containing 4,194,304 bits organized in a x4 configuration. During READ or WRITE cycles each bit is uniquely addressed through the 20 address bits which are entered 10 bits (A0-A9) at a time. RAS is used to latch the fir | AUSTIN | | ||
1 MEG x 4 DRAM Fast Page Mode DRAM GENERAL DESCRIPTION The MT4C4001J is a randomly accessed solid-state memory containing 4,194,304 bits organized in a x4 configuration. During READ or WRITE cycles each bit is uniquely addressed through the 20 address bits which are entered 10 bits (A0-A9) at a time. RAS is used to latch the fir | AUSTIN | | ||
1 MEG x 4 DRAM Fast Page Mode DRAM GENERAL DESCRIPTION The MT4C4001J is a randomly accessed solid-state memory containing 4,194,304 bits organized in a x4 configuration. During READ or WRITE cycles each bit is uniquely addressed through the 20 address bits which are entered 10 bits (A0-A9) at a time. RAS is used to latch the fir | AUSTIN | | ||
1 MEG x 4 DRAM Fast Page Mode DRAM GENERAL DESCRIPTION The MT4C4001J is a randomly accessed solid-state memory containing 4,194,304 bits organized in a x4 configuration. During READ or WRITE cycles each bit is uniquely addressed through the 20 address bits which are entered 10 bits (A0-A9) at a time. RAS is used to latch the fir | AUSTIN | | ||
1 MEG x 4 DRAM Fast Page Mode DRAM GENERAL DESCRIPTION The MT4C4001J is a randomly accessed solid-state memory containing 4,194,304 bits organized in a x4 configuration. During READ or WRITE cycles each bit is uniquely addressed through the 20 address bits which are entered 10 bits (A0-A9) at a time. RAS is used to latch the fir | AUSTIN | | ||
1 MEG x 4 DRAM Fast Page Mode DRAM GENERAL DESCRIPTION The MT4C4001J is a randomly accessed solid-state memory containing 4,194,304 bits organized in a x4 configuration. During READ or WRITE cycles each bit is uniquely addressed through the 20 address bits which are entered 10 bits (A0-A9) at a time. RAS is used to latch the fir | AUSTIN | | ||
1 MEG x 4 DRAM Fast Page Mode DRAM GENERAL DESCRIPTION The MT4C4001J is a randomly accessed solid-state memory containing 4,194,304 bits organized in a x4 configuration. During READ or WRITE cycles each bit is uniquely addressed through the 20 address bits which are entered 10 bits (A0-A9) at a time. RAS is used to latch the fir | AUSTIN | | ||
1 MEG x 4 DRAM Fast Page Mode DRAM GENERAL DESCRIPTION The MT4C4001J is a randomly accessed solid-state memory containing 4,194,304 bits organized in a x4 configuration. During READ or WRITE cycles each bit is uniquely addressed through the 20 address bits which are entered 10 bits (A0-A9) at a time. RAS is used to latch the fir | AUSTIN | | ||
1 MEG x 4 DRAM Fast Page Mode DRAM GENERAL DESCRIPTION The MT4C4001J is a randomly accessed solid-state memory containing 4,194,304 bits organized in a x4 configuration. During READ or WRITE cycles each bit is uniquely addressed through the 20 address bits which are entered 10 bits (A0-A9) at a time. RAS is used to latch the fir | AUSTIN | | ||
1 MEG x 4 DRAM Fast Page Mode DRAM GENERAL DESCRIPTION The MT4C4001J is a randomly accessed solid-state memory containing 4,194,304 bits organized in a x4 configuration. During READ or WRITE cycles each bit is uniquely addressed through the 20 address bits which are entered 10 bits (A0-A9) at a time. RAS is used to latch the fir | AUSTIN | | ||
1 MEG x 4 DRAM Fast Page Mode DRAM GENERAL DESCRIPTION The MT4C4001J is a randomly accessed solid-state memory containing 4,194,304 bits organized in a x4 configuration. During READ or WRITE cycles each bit is uniquely addressed through the 20 address bits which are entered 10 bits (A0-A9) at a time. RAS is used to latch the fir | AUSTIN | | ||
1 MEG x 4 DRAM Fast Page Mode DRAM GENERAL DESCRIPTION The MT4C4001J is a randomly accessed solid-state memory containing 4,194,304 bits organized in a x4 configuration. During READ or WRITE cycles each bit is uniquely addressed through the 20 address bits which are entered 10 bits (A0-A9) at a time. RAS is used to latch the fir | AUSTIN | | ||
1 MEG x 4 DRAM Fast Page Mode DRAM GENERAL DESCRIPTION The MT4C4001J is a randomly accessed solid-state memory containing 4,194,304 bits organized in a x4 configuration. During READ or WRITE cycles each bit is uniquely addressed through the 20 address bits which are entered 10 bits (A0-A9) at a time. RAS is used to latch the fir | AUSTIN | | ||
1 MEG x 4 DRAM Fast Page Mode DRAM GENERAL DESCRIPTION The MT4C4001J is a randomly accessed solid-state memory containing 4,194,304 bits organized in a x4 configuration. During READ or WRITE cycles each bit is uniquely addressed through the 20 address bits which are entered 10 bits (A0-A9) at a time. RAS is used to latch the fir | AUSTIN | | ||
1 MEG x 4 DRAM Fast Page Mode DRAM GENERAL DESCRIPTION The MT4C4001J is a randomly accessed solid-state memory containing 4,194,304 bits organized in a x4 configuration. During READ or WRITE cycles each bit is uniquely addressed through the 20 address bits which are entered 10 bits (A0-A9) at a time. RAS is used to latch the fir | AUSTIN | | ||
1 MEG x 4 DRAM Fast Page Mode DRAM GENERAL DESCRIPTION The MT4C4001J is a randomly accessed solid-state memory containing 4,194,304 bits organized in a x4 configuration. During READ or WRITE cycles each bit is uniquely addressed through the 20 address bits which are entered 10 bits (A0-A9) at a time. RAS is used to latch the fir | AUSTIN | | ||
1 MEG x 4 DRAM Fast Page Mode DRAM GENERAL DESCRIPTION The MT4C4001J is a randomly accessed solid-state memory containing 4,194,304 bits organized in a x4 configuration. During READ or WRITE cycles each bit is uniquely addressed through the 20 address bits which are entered 10 bits (A0-A9) at a time. RAS is used to latch the fir | AUSTIN | | ||
1 MEG x 4 DRAM Fast Page Mode DRAM GENERAL DESCRIPTION The MT4C4001J is a randomly accessed solid-state memory containing 4,194,304 bits organized in a x4 configuration. During READ or WRITE cycles each bit is uniquely addressed through the 20 address bits which are entered 10 bits (A0-A9) at a time. RAS is used to latch the fir | AUSTIN | | ||
1 MEG x 4 DRAM Fast Page Mode DRAM GENERAL DESCRIPTION The MT4C4001J is a randomly accessed solid-state memory containing 4,194,304 bits organized in a x4 configuration. During READ or WRITE cycles each bit is uniquely addressed through the 20 address bits which are entered 10 bits (A0-A9) at a time. RAS is used to latch the fir | AUSTIN | | ||
1 MEG x 4 DRAM Fast Page Mode DRAM GENERAL DESCRIPTION The MT4C4001J is a randomly accessed solid-state memory containing 4,194,304 bits organized in a x4 configuration. During READ or WRITE cycles each bit is uniquely addressed through the 20 address bits which are entered 10 bits (A0-A9) at a time. RAS is used to latch the fir | AUSTIN | | ||
1 MEG x 4 DRAM Fast Page Mode DRAM GENERAL DESCRIPTION The MT4C4001J is a randomly accessed solid-state memory containing 4,194,304 bits organized in a x4 configuration. During READ or WRITE cycles each bit is uniquely addressed through the 20 address bits which are entered 10 bits (A0-A9) at a time. RAS is used to latch the fir | AUSTIN | | ||
1 MEG x 4 DRAM Fast Page Mode DRAM GENERAL DESCRIPTION The MT4C4001J is a randomly accessed solid-state memory containing 4,194,304 bits organized in a x4 configuration. During READ or WRITE cycles each bit is uniquely addressed through the 20 address bits which are entered 10 bits (A0-A9) at a time. RAS is used to latch the fir | AUSTIN | | ||
1 MEG x 4 DRAM Fast Page Mode DRAM GENERAL DESCRIPTION The MT4C4001J is a randomly accessed solid-state memory containing 4,194,304 bits organized in a x4 configuration. During READ or WRITE cycles each bit is uniquely addressed through the 20 address bits which are entered 10 bits (A0-A9) at a time. RAS is used to latch the fir | AUSTIN | | ||
1 MEG x 4 DRAM Fast Page Mode DRAM GENERAL DESCRIPTION The MT4C4001J is a randomly accessed solid-state memory containing 4,194,304 bits organized in a x4 configuration. During READ or WRITE cycles each bit is uniquely addressed through the 20 address bits which are entered 10 bits (A0-A9) at a time. RAS is used to latch the fir | AUSTIN | | ||
1 MEG x 4 DRAM Fast Page Mode DRAM GENERAL DESCRIPTION The MT4C4001J is a randomly accessed solid-state memory containing 4,194,304 bits organized in a x4 configuration. During READ or WRITE cycles each bit is uniquely addressed through the 20 address bits which are entered 10 bits (A0-A9) at a time. RAS is used to latch the fir | AUSTIN | | ||
1 MEG x 4 DRAM Fast Page Mode DRAM GENERAL DESCRIPTION The MT4C4001J is a randomly accessed solid-state memory containing 4,194,304 bits organized in a x4 configuration. During READ or WRITE cycles each bit is uniquely addressed through the 20 address bits which are entered 10 bits (A0-A9) at a time. RAS is used to latch the fir | AUSTIN | | ||
1 MEG x 4 DRAM Fast Page Mode DRAM GENERAL DESCRIPTION The MT4C4001J is a randomly accessed solid-state memory containing 4,194,304 bits organized in a x4 configuration. During READ or WRITE cycles each bit is uniquely addressed through the 20 address bits which are entered 10 bits (A0-A9) at a time. RAS is used to latch the fir | AUSTIN | | ||
1 MEG x 4 DRAM Fast Page Mode DRAM GENERAL DESCRIPTION The MT4C4001J is a randomly accessed solid-state memory containing 4,194,304 bits organized in a x4 configuration. During READ or WRITE cycles each bit is uniquely addressed through the 20 address bits which are entered 10 bits (A0-A9) at a time. RAS is used to latch the fir | AUSTIN | | ||
1 MEG x 4 DRAM Fast Page Mode DRAM GENERAL DESCRIPTION The MT4C4001J is a randomly accessed solid-state memory containing 4,194,304 bits organized in a x4 configuration. During READ or WRITE cycles each bit is uniquely addressed through the 20 address bits which are entered 10 bits (A0-A9) at a time. RAS is used to latch the fir | AUSTIN | | ||
1 MEG x 4 DRAM Fast Page Mode DRAM GENERAL DESCRIPTION The MT4C4001J is a randomly accessed solid-state memory containing 4,194,304 bits organized in a x4 configuration. During READ or WRITE cycles each bit is uniquely addressed through the 20 address bits which are entered 10 bits (A0-A9) at a time. RAS is used to latch the fir | AUSTIN | | ||
1 MEG x 4 DRAM Fast Page Mode DRAM GENERAL DESCRIPTION The MT4C4001J is a randomly accessed solid-state memory containing 4,194,304 bits organized in a x4 configuration. During READ or WRITE cycles each bit is uniquely addressed through the 20 address bits which are entered 10 bits (A0-A9) at a time. RAS is used to latch the fir | AUSTIN | | ||
1 MEG x 4 DRAM Fast Page Mode DRAM GENERAL DESCRIPTION The MT4C4001J is a randomly accessed solid-state memory containing 4,194,304 bits organized in a x4 configuration. During READ or WRITE cycles each bit is uniquely addressed through the 20 address bits which are entered 10 bits (A0-A9) at a time. RAS is used to latch the fir | AUSTIN | | ||
1 MEG x 4 DRAM Fast Page Mode DRAM GENERAL DESCRIPTION The MT4C4001J is a randomly accessed solid-state memory containing 4,194,304 bits organized in a x4 configuration. During READ or WRITE cycles each bit is uniquely addressed through the 20 address bits which are entered 10 bits (A0-A9) at a time. RAS is used to latch the fir | AUSTIN | | ||
1 MEG x 4 DRAM Fast Page Mode DRAM GENERAL DESCRIPTION The MT4C4001J is a randomly accessed solid-state memory containing 4,194,304 bits organized in a x4 configuration. During READ or WRITE cycles each bit is uniquely addressed through the 20 address bits which are entered 10 bits (A0-A9) at a time. RAS is used to latch the fir | AUSTIN | | ||
1 MEG x 4 DRAM Fast Page Mode DRAM GENERAL DESCRIPTION The MT4C4001J is a randomly accessed solid-state memory containing 4,194,304 bits organized in a x4 configuration. During READ or WRITE cycles each bit is uniquely addressed through the 20 address bits which are entered 10 bits (A0-A9) at a time. RAS is used to latch the fir | AUSTIN | | ||
1 MEG x 4 DRAM Fast Page Mode DRAM GENERAL DESCRIPTION The MT4C4001J is a randomly accessed solid-state memory containing 4,194,304 bits organized in a x4 configuration. During READ or WRITE cycles each bit is uniquely addressed through the 20 address bits which are entered 10 bits (A0-A9) at a time. RAS is used to latch the fir | AUSTIN | | ||
1 MEG x 4 DRAM Fast Page Mode DRAM GENERAL DESCRIPTION The MT4C4001J is a randomly accessed solid-state memory containing 4,194,304 bits organized in a x4 configuration. During READ or WRITE cycles each bit is uniquely addressed through the 20 address bits which are entered 10 bits (A0-A9) at a time. RAS is used to latch the fir | AUSTIN | | ||
1 MEG x 4 DRAM Fast Page Mode DRAM GENERAL DESCRIPTION The MT4C4001J is a randomly accessed solid-state memory containing 4,194,304 bits organized in a x4 configuration. During READ or WRITE cycles each bit is uniquely addressed through the 20 address bits which are entered 10 bits (A0-A9) at a time. RAS is used to latch the fir | AUSTIN | | ||
1 MEG x 4 DRAM Fast Page Mode DRAM GENERAL DESCRIPTION The MT4C4001J is a randomly accessed solid-state memory containing 4,194,304 bits organized in a x4 configuration. During READ or WRITE cycles each bit is uniquely addressed through the 20 address bits which are entered 10 bits (A0-A9) at a time. RAS is used to latch the fir | AUSTIN | | ||
1 MEG x 4 DRAM Fast Page Mode DRAM GENERAL DESCRIPTION The MT4C4001J is a randomly accessed solid-state memory containing 4,194,304 bits organized in a x4 configuration. During READ or WRITE cycles each bit is uniquely addressed through the 20 address bits which are entered 10 bits (A0-A9) at a time. RAS is used to latch the fir | AUSTIN | |
MT4C4001J产品属性
- 类型
描述
- 型号
MT4C4001J
- 制造商
AUSTIN
- 制造商全称
Austin Semiconductor
- 功能描述
1 MEG x 4 DRAM Fast Page Mode DRAM
| IC供应商 | 芯片型号 | 品牌 | 批号 | 封装 | 库存 | 备注 | 价格 |
|---|---|---|---|---|---|---|---|
Micron(镁光) |
25+ |
N/A |
18798 |
原装正品现货,原厂订货,可支持含税原型号开票。 |
|||
ASI |
24+ |
CDIP |
1500 |
AI芯片,车规MCU原装现货/为新能源汽车电子行业采购保驾护航 |
|||
MCT |
24+/25+ |
48 |
原装正品现货库存价优 |
||||
原厂 |
2540+ |
CDIP20 |
6852 |
只做原装正品假一赔十为客户做到零风险!! |
|||
MICRON |
95+ |
SOJ20 |
67 |
一级代理,专注军工、汽车、医疗、工业、新能源、电力 |
|||
MICRON |
25+ |
SOJ16 |
10000 |
原装现货 |
|||
24+ |
SOJ20 |
35210 |
一级代理/放心采购 |
||||
ASI |
24+ |
CDIP |
200 |
进口原装正品优势供应 |
|||
MICRON/美光 |
26+ |
SOJ20 |
1149 |
一级代理优势现货,全新正品直营店 |
|||
MIC |
25+ |
NA |
661 |
专做原装正品,假一罚百! |
MT4C4001J芯片相关品牌
MT4C4001J规格书下载地址
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