3-to-8 Line Decoder With Address Latches (Inverted Output)

文件：131.58 Kbytes Page：6 Pages

3-to-8 Line Decoder With Address Latches (Inverted Output)

3-to-8 Line Decoder With Address Latches (Inverted Output)

文件：131.58 Kbytes Page：6 Pages

3-to-8 Line Decoder With Address Latches (Inverted Output)

文件：131.58 Kbytes Page：6 Pages

3-to-8 line decoder/demultiplexer with address latches; inverting

GENERAL DESCRIPTION The 74HC/HCT137 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Combines 3-to-8 decoder with 3-bit latch • Multiple input enable for easy expansion or ind

3-to-8 line decoder, demultiplexer with address latches; inverting

1. General description The 74HC137 decodes three binary weighted address inputs (A0, A1 and A2) to eight mutually exclusive outputs (Y0 to Y7). The device features a latch enable (LE) and two output enable (E1, E2) inputs. A LOW on LE causes the device to act as an active LOW decoder. A LOW-to

3-to-8 line decoder, demultiplexer with address latches inverting

文件：107.6 Kbytes Page：19 Pages

3-to-8 line decoder/demultiplexer with address latches; inverting

文件：72.22 Kbytes Page：8 Pages

3-to-8 line decoder, demultiplexer with address latches inverting

文件：107.6 Kbytes Page：19 Pages