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74HC137价格

参考价格:¥1.0432

型号:74HC137D,652 品牌:NXP 备注:这里有74HC137多少钱,2026年最近7天走势,今日出价,今日竞价,74HC137批发/采购报价,74HC137行情走势销售排行榜,74HC137报价。
型号 功能描述 生产厂家 企业 LOGO 操作
74HC137

3-to-8 line decoder/demultiplexer with address latches; inverting

GENERAL DESCRIPTION The 74HC/HCT137 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Combines 3-to-8 decoder with 3-bit latch • Multiple input enable for easy expansion or ind

PHILIPS

飞利浦

74HC137

3-to-8 line decoder, demultiplexer with address latches; inverting

1. General description The 74HC137 decodes three binary weighted address inputs (A0, A1 and A2) to eight mutually exclusive outputs (Y0 to Y7). The device features a latch enable (LE) and two output enable (E1, E2) inputs. A LOW on LE causes the device to act as an active LOW decoder. A LOW-to

NEXPERIA

安世

74HC137

3-to-8 line decoder, demultiplexer with address latches inverting

文件:107.6 Kbytes Page:19 Pages

PHILIPS

飞利浦

74HC137

3-to-8 line decoder/demultiplexer with address latches; inverting

文件:72.22 Kbytes Page:8 Pages

PHILIPS

飞利浦

3-to-8 line decoder, demultiplexer with address latches; inverting

1. General description The 74HC137 decodes three binary weighted address inputs (A0, A1 and A2) to eight mutually exclusive outputs (Y0 to Y7). The device features a latch enable (LE) and two output enable (E1, E2) inputs. A LOW on LE causes the device to act as an active LOW decoder. A LOW-to

NEXPERIA

安世

3-to-8 line decoder, demultiplexer with address latches; inverting

The 74HC137 is a high-speed Si-gate CMOS device and is pin compatible with low power Schottky TTL (LSTTL). The 74HC137 is specified in compliance with JEDEC standard no. 7A.\n The 74HC137 is a 3-to-8 line decoder, demultiplexer with latches at the three address inputs (An). The 74HC137 essentiall • Combines 3-to-8 decoder with 3-bit latch\n• Multiple input enable for easy expansion or independent controls\n• Active LOW mutually exclusive outputs\n• Low-power dissipation\n• Complies with JEDEC standard no. 7A\n• ESD protection:• HBM EIA/JESD22-A114-B exceeds 2000 V\n• MM EIA/JESD22-A115-A exc;

NEXPERIA

安世

3-to-8 line decoder, demultiplexer with address latches; inverting

The 74HC137 is a high-speed Si-gate CMOS device and is pin compatible with low power Schottky TTL (LSTTL). The 74HC137 is specified in compliance with JEDEC standard no. 7A.\n The 74HC137 is a 3-to-8 line decoder, demultiplexer with latches at the three address inputs (An). The 74HC137 essentiall • Combines 3-to-8 decoder with 3-bit latch\n• Multiple input enable for easy expansion or independent controls\n• Active LOW mutually exclusive outputs\n• Low-power dissipation\n• Complies with JEDEC standard no. 7A\n• ESD protection:• HBM EIA/JESD22-A114-B exceeds 2000 V\n• MM EIA/JESD22-A115-A exc;

NEXPERIA

安世

3-to-8 line decoder, demultiplexer with address latches; inverting

1. General description The 74HC137 decodes three binary weighted address inputs (A0, A1 and A2) to eight mutually exclusive outputs (Y0 to Y7). The device features a latch enable (LE) and two output enable (E1, E2) inputs. A LOW on LE causes the device to act as an active LOW decoder. A LOW-to

NEXPERIA

安世

3-to-8 line decoder, demultiplexer with address latches; inverting

1. General description The 74HC137 decodes three binary weighted address inputs (A0, A1 and A2) to eight mutually exclusive outputs (Y0 to Y7). The device features a latch enable (LE) and two output enable (E1, E2) inputs. A LOW on LE causes the device to act as an active LOW decoder. A LOW-to

NEXPERIA

安世

3-to-8 line decoder, demultiplexer with address latches; inverting

The 74HC137 decodes three binary weighted address inputs (A0, A1 and A2) to eight mutually exclusive outputs (Y0 to Y7). The device features a latch enable (LE) and two output enable (E1, E2) inputs. A LOW on LE causes the device to act as an active LOW decoder. A LOW-to HIGH transition on LE stores • Combines 3-to-8 decoder with 3-bit latch\n• Multiple input enable for easy expansion or independent controls\n• Active LOW mutually exclusive outputs\n• Wide supply voltage range from 2.0 to 6.0 V\n• CMOS low power dissipation\n• High noise immunity\n• Latch-up performance exceeds 100 mA per JESD ;

NEXPERIA

安世

3-to-8 line decoder/demultiplexer with address latches; inverting

文件:72.22 Kbytes Page:8 Pages

PHILIPS

飞利浦

3-to-8 line decoder, demultiplexer with address latches; inverting

文件:114.83 Kbytes Page:19 Pages

PHILIPS

飞利浦

3-to-8 line decoder, demultiplexer with address latches inverting

文件:107.6 Kbytes Page:19 Pages

PHILIPS

飞利浦

封装/外壳:16-SOIC(0.154",3.90mm 宽) 包装:卷带(TR)剪切带(CT)Digi-Reel® 得捷定制卷带 描述:IC DECODER/DEMUX 1 X 3:8 16SO 集成电路(IC) 信号开关,多路复用器,解码器

ETC

知名厂家

3-to-8 line decoder, demultiplexer with address latches inverting

文件:107.6 Kbytes Page:19 Pages

PHILIPS

飞利浦

封装/外壳:16-SSOP(0.209",5.30mm 宽) 包装:托盘 描述:IC DECODER/DEMUX 1X3:8 16SSOP 集成电路(IC) 信号开关,多路复用器,解码器

ETC

知名厂家

3-to-8 line decoder, demultiplexer with address latches inverting

文件:107.6 Kbytes Page:19 Pages

PHILIPS

飞利浦

3 TO 8 LINE DECODER/LATCH INVERTING

DESCRIPTION TheM54/74HC137 is ahigh speed CMOS3TO8LINE DECODER/LATCH (INVERTING) fabricated in silicon gate C2MOS technology. It has the same high speed performance of LSTTL combined with true CMOS low power consumption. ■ HIGH SPEED tPD = 11 ns (TYP.) AT VCC = 5 V ■ LOW POWER DISSIPATION ICC

STMICROELECTRONICS

意法半导体

High Speed CMOS Logic, 3-to-8 Line Decoder Demultiplexer with Address Latches

文件:65.099 Kbytes Page:10 Pages

TI

德州仪器

High Speed CMOS Logic, 3-to-8 Line Decoder Demultiplexer with Address Latches

文件:65.099 Kbytes Page:10 Pages

TI

德州仪器

High-Speed CMOS Logic, 3- to 8-Line Decoder/Demultiplexer with Address Latches

文件:381.06 Kbytes Page:16 Pages

TI

德州仪器

74HC137产品属性

  • 类型

    描述

  • VCC (V):

    2.0 - 6.0

  • Logic switching levels:

    CMOS

  • Output drive capability (mA):

    ± 5.2

  • tpd (ns):

    18

  • Power dissipation considerations:

    low

  • Tamb (°C):

    -40~125

  • Rth(j-a) (K/W):

    72

  • Ψth(j-top) (K/W):

    1.0

  • Rth(j-c) (K/W):

    30

  • Package name:

    SO16

更新时间:2026-5-18 9:21:00
IC供应商 芯片型号 品牌 批号 封装 库存 备注 价格
PHI
24+
SOP
80000
只做自己库存 全新原装进口正品假一赔百 可开13%增
Nexperia USA Inc.
24+25+
16500
全新原厂原装现货!受权代理!可送样可提供技术支持!
MAX
23+24
N/A
27960
原装现货.优势热卖.终端BOM表可配单
PHIL
24+/25+
1000
原装正品现货库存价优
PHI
2023+
PDIP16
6893
十五年行业诚信经营,专注全新正品
PHI
25+
SOP
3200
全新原装、诚信经营、公司现货销售
恩XP
25+
SOP
90000
全新原装现货
恩XP
25+
SOT-353
10000
原装优势现货
NEXPERIA/安世
25+
SOT109-1
50000
全新原装现货库存
PHI
2023+
DIP-16
58000
进口原装,现货热卖

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