HIGH-SPEED CMOS LOGIC OCTAL D-TYPE FLIP-FLOP 3-STATE, POSITIVE-EDGE TRIGGERED

Controlled Baseline − One Assembly/Test Site, One Fabrication Site Extended Temperature Performance of −40°C to 125°C Enhanced Diminishing Manufacturing Sources (DMS) Support Enhanced Product Change Notification Qualification Pedigree† Buffered Inputs Common 3-State Output-Enable Control

HIGH-SPEED CMOS LOGIC OCTAL D-TYPE FLIP-FLOP 3-STATE, POSITIVE-EDGE TRIGGERED

Qualified for Automotive Applications Buffered Inputs Common 3-State Output-Enable Control 3-State Outputs Bus-Line Driving Capability Typical Propagation Delay (Clock to Q): 15 ns at VCC = 5 V, CL = 15 pF, TA = 25
C Fanout (Over Temperature Range) Standard Outputs . . . 10 LSTTL Loads Bu

High-Speed CMOS Logic Octal D-Type Flip-Flop, 3-State Positive-Edge Triggered

文件：454.51 Kbytes Page：18 Pages

High-Speed CMOS Logic Octal D-Type Flip-Flop, 3-State Positive-Edge Triggered

文件：48.7 Kbytes Page：8 Pages

High-Speed CMOS Logic Octal D-Type Flip-Flop, 3-State Positive-Edge Triggered

文件：454.51 Kbytes Page：18 Pages