DOT MATRIX LCD CONTROLLER DRIVER

GENERAL DESCRIPTION The ML9041A used in combination with an 8-bit or 4-bit microcontroller controls the operation of a character type dot matrix LCD. FEATURES • Easy interfacing with 8-bit or 4-bit microcontroller • Switchable between serial and parallel interfaces • Dot-matrix LC

DOT MATRIX LCD CONTROLLER DRIVER

DOT MATRIX LCD CONTROLLER DRIVER

GENERAL DESCRIPTION The ML9041A used in combination with an 8-bit or 4-bit microcontroller controls the operation of a character type dot matrix LCD. FEATURES • Easy interfacing with 8-bit or 4-bit microcontroller • Switchable between serial and parallel interfaces • Dot-matrix LC

DOT MATRIX LCD CONTROLLER DRIVER

GENERAL DESCRIPTION The ML9041A used in combination with an 8-bit or 4-bit microcontroller controls the operation of a character type dot matrix LCD. FEATURES • Easy interfacing with 8-bit or 4-bit microcontroller • Switchable between serial and parallel interfaces • Dot-matrix LC

DOT MATRIX LCD CONTROLLER DRIVER

Micropower, Single-Supply, UCSP/SOT23 Comparator Precision Reference ICs

General Description The MAX9038–MAX9043 and MAX9050–MAX9053 feature combinations of low-power comparators and precision voltage references. Their operating voltage range makes them ideal for both 3V and 5V systems. Features ● Comparator + Precision Reference in UCSP/SOT23 ● 2.5V to 5.5V Single

Multiple Output Trunk PLL

Description The MT9041 is a digital phase-locked loop (PLL) designed to provide timing and synchronization signals for T1 and E1 primary rate transmission links that are compatible with ST-BUS/GCI frame alignment timing requirements. The PLL outputs can be synchronized to either a 2.048 MHz, 1.

Multiple Output Trunk PLL

Description The MT9041 is a digital phase-locked loop (PLL) designed to provide timing and synchronization signals for T1 and E1 primary rate transmission links that are compatible with ST-BUS/GCI frame alignment timing requirements. The PLL outputs can be synchronized to either a 2.048 MHz, 1.

T1/E1 System Synchronizer

Description The MT9041B T1/E1 System Synchronizer contains a digital phase-locked loop (DPLL), which provides timing and synchronization signals for multitrunk T1 and E1 primary rate transmission links. The MT9041B generates ST-BUS clock and framing signals that are phase locked to either a

T1/E1 System Synchronizer

Description The MT9041B T1/E1 System Synchronizer contains a digital phase-locked loop (DPLL), which provides timing and synchronization signals for multitrunk T1 and E1 primary rate transmission links. The MT9041B generates ST-BUS clock and framing signals that are phase locked to either a