Frame Rate Communications PLL

Description The MK1574-01 is a Phase-Locked Loop (PLL) based clock synthesizer, which accepts an 8 kHz clock input as a reference, and generates many popular communications frequencies. All outputs are frequency locked together and to the input. This allows for the generation of locked clocks to

3.3 VOLT FRAME RATE COMMUNICATIONS PLL

Features • 3.3 volt operation • Packaged in 16-pin SOIC • Accepts 8 kHz input clock • Output clock rates include T1, E1, T2, E2 • Available in commercial (0º to + 70ºC) or industrial (-40 to +85ºC) temperature ranges • Available in Pb (lead) free package • For jitter attenuation, use the M

Frame Rate Communications PLL

丝印代码：MK1574-01S；3.3 VOLT FRAME RATE COMMUNICATIONS PLL

Features • 3.3 volt operation • Packaged in 16-pin SOIC • Accepts 8 kHz input clock • Output clock rates include T1, E1, T2, E2 • Available in commercial (0º to + 70ºC) or industrial (-40 to +85ºC) temperature ranges • Available in Pb (lead) free package • For jitter attenuation, use the M

丝印代码：MK1574-01SI；3.3 VOLT FRAME RATE COMMUNICATIONS PLL

Features • 3.3 volt operation • Packaged in 16-pin SOIC • Accepts 8 kHz input clock • Output clock rates include T1, E1, T2, E2 • Available in commercial (0º to + 70ºC) or industrial (-40 to +85ºC) temperature ranges • Available in Pb (lead) free package • For jitter attenuation, use the M

丝印代码：MK1574-01SILF；3.3 VOLT FRAME RATE COMMUNICATIONS PLL

Features • 3.3 volt operation • Packaged in 16-pin SOIC • Accepts 8 kHz input clock • Output clock rates include T1, E1, T2, E2 • Available in commercial (0º to + 70ºC) or industrial (-40 to +85ºC) temperature ranges • Available in Pb (lead) free package • For jitter attenuation, use the M

丝印代码：MK1574-01SILF；3.3 VOLT FRAME RATE COMMUNICATIONS PLL

Features • 3.3 volt operation • Packaged in 16-pin SOIC • Accepts 8 kHz input clock • Output clock rates include T1, E1, T2, E2 • Available in commercial (0º to + 70ºC) or industrial (-40 to +85ºC) temperature ranges • Available in Pb (lead) free package • For jitter attenuation, use the M

丝印代码：MK1574-01SI；3.3 VOLT FRAME RATE COMMUNICATIONS PLL

Features • 3.3 volt operation • Packaged in 16-pin SOIC • Accepts 8 kHz input clock • Output clock rates include T1, E1, T2, E2 • Available in commercial (0º to + 70ºC) or industrial (-40 to +85ºC) temperature ranges • Available in Pb (lead) free package • For jitter attenuation, use the M

丝印代码：MK1574-01SLF；3.3 VOLT FRAME RATE COMMUNICATIONS PLL

Features • 3.3 volt operation • Packaged in 16-pin SOIC • Accepts 8 kHz input clock • Output clock rates include T1, E1, T2, E2 • Available in commercial (0º to + 70ºC) or industrial (-40 to +85ºC) temperature ranges • Available in Pb (lead) free package • For jitter attenuation, use the M

丝印代码：MK1574-01SLF；3.3 VOLT FRAME RATE COMMUNICATIONS PLL

Features • 3.3 volt operation • Packaged in 16-pin SOIC • Accepts 8 kHz input clock • Output clock rates include T1, E1, T2, E2 • Available in commercial (0º to + 70ºC) or industrial (-40 to +85ºC) temperature ranges • Available in Pb (lead) free package • For jitter attenuation, use the M

丝印代码：MK1574-01S；3.3 VOLT FRAME RATE COMMUNICATIONS PLL

Features • 3.3 volt operation • Packaged in 16-pin SOIC • Accepts 8 kHz input clock • Output clock rates include T1, E1, T2, E2 • Available in commercial (0º to + 70ºC) or industrial (-40 to +85ºC) temperature ranges • Available in Pb (lead) free package • For jitter attenuation, use the M

Frame Rate Communications PLL

The MK1574-01 is a Phase-Locked Loop (PLL) based clock synthesizer, which accepts an 8 kHz clock input as a reference, and generates many popular communications frequencies. All outputs are frequency locked together and to the input. This allows for the generation of locked clocks to the 8 kHz backp 3.3 volt operation\nPackaged in 16-pin SOIC\nAvailable in Pb (lead) free package\nAccepts 8 kHz input clock\nOutput clock rates include T1, E1, T2, E2\nAvailable in commercial (0;

丝印代码：157401ASLF；FRAME RATE COMMUNICATIONS PLL

Features • Packaged in 16-pin SOIC • Accepts 8 kHz input clock • Output clock rates include T1, E1, T2, E2 • Available in commercial (0º to + 70ºC) or industrial (-40 to +85ºC) temperature ranges • For jitter attenuation, use the MK2049

丝印代码：157401ASLF；FRAME RATE COMMUNICATIONS PLL

Features • Packaged in 16-pin SOIC • Accepts 8 kHz input clock • Output clock rates include T1, E1, T2, E2 • Available in commercial (0º to + 70ºC) or industrial (-40 to +85ºC) temperature ranges • For jitter attenuation, use the MK2049

丝印代码：157401ASLF；FRAME RATE COMMUNICATIONS PLL

Features • Packaged in 16-pin SOIC • Accepts 8 kHz input clock • Output clock rates include T1, E1, T2, E2 • Available in commercial (0º to + 70ºC) or industrial (-40 to +85ºC) temperature ranges • For jitter attenuation, use the MK2049

丝印代码：157401ASLF；FRAME RATE COMMUNICATIONS PLL

Features • Packaged in 16-pin SOIC • Accepts 8 kHz input clock • Output clock rates include T1, E1, T2, E2 • Available in commercial (0º to + 70ºC) or industrial (-40 to +85ºC) temperature ranges • For jitter attenuation, use the MK2049

FRAME RATE COMMUNICATIONS PLL

Features • Packaged in 16-pin SOIC • Accepts 8 kHz input clock • Output clock rates include T1, E1, T2, E2 • Available in commercial (0º to + 70ºC) or industrial (-40 to +85ºC) temperature ranges • For jitter attenuation, use the MK2049

Frame Rate Communications PLL

The MK1574-01A/B are Phase-Locked Loop (PLL) based clock synthesizers that accept an 8kHz clock input as a reference and generate many popular communications frequencies. All outputs are frequency-locked together and to the input. This allows for the generation of locked clocks to the 8kHz backplane • Packaged in a 16-pin SOIC\n• Output clock rates include T1, E1, T2, and E2\n• Available in commercial (0 °C to + 70 °C) or industrial (-40 °C to +85 °C) temperature ranges;

丝印代码：157401ASLF；FRAME RATE COMMUNICATIONS PLL

Features • Packaged in 16-pin SOIC • Accepts 8 kHz input clock • Output clock rates include T1, E1, T2, E2 • Available in commercial (0º to + 70ºC) or industrial (-40 to +85ºC) temperature ranges • For jitter attenuation, use the MK2049

丝印代码：157401ASLF；FRAME RATE COMMUNICATIONS PLL

Features • Packaged in 16-pin SOIC • Accepts 8 kHz input clock • Output clock rates include T1, E1, T2, E2 • Available in commercial (0º to + 70ºC) or industrial (-40 to +85ºC) temperature ranges • For jitter attenuation, use the MK2049

丝印代码：157401ASLF；FRAME RATE COMMUNICATIONS PLL

Features • Packaged in 16-pin SOIC • Accepts 8 kHz input clock • Output clock rates include T1, E1, T2, E2 • Available in commercial (0º to + 70ºC) or industrial (-40 to +85ºC) temperature ranges • For jitter attenuation, use the MK2049

丝印代码：157401ASLF；FRAME RATE COMMUNICATIONS PLL

Features • Packaged in 16-pin SOIC • Accepts 8 kHz input clock • Output clock rates include T1, E1, T2, E2 • Available in commercial (0º to + 70ºC) or industrial (-40 to +85ºC) temperature ranges • For jitter attenuation, use the MK2049

Frame Rate Communications PLL

Description The MK1574-01 is a Phase-Locked Loop (PLL) based clock synthesizer, which accepts an 8 kHz clock input as a reference, and generates many popular communications frequencies. All outputs are frequency locked together and to the input. This allows for the generation of locked clocks to

Frame Rate Communications PLL

Description The MK1574-01 is a Phase-Locked Loop (PLL) based clock synthesizer, which accepts an 8 kHz clock input as a reference, and generates many popular communications frequencies. All outputs are frequency locked together and to the input. This allows for the generation of locked clocks to

Frame Rate Communications PLL

Description The MK1574-01 is a Phase-Locked Loop (PLL) based clock synthesizer, which accepts an 8 kHz clock input as a reference, and generates many popular communications frequencies. All outputs are frequency locked together and to the input. This allows for the generation of locked clocks to

Frame Rate Communications PLL

Description The MK1574-01 is a Phase-Locked Loop (PLL) based clock synthesizer, which accepts an 8 kHz clock input as a reference, and generates many popular communications frequencies. All outputs are frequency locked together and to the input. This allows for the generation of locked clocks to

封装/外壳：16-SOIC（0.154"，3.90mm 宽） 包装：管件 描述：IC PLL FRAME RATE COMM 16-SOIC 集成电路（IC） 时钟发生器，PLL，频率合成器

封装/外壳：16-SOIC（0.154"，3.90mm 宽） 包装：管件 描述：IC PLL FRAME RATE COMM 16-SOIC 集成电路（IC） 时钟发生器，PLL，频率合成器

Phase Control Thyristor

FEATURES ■ Double Side Cooling. ■ High Surge Capability. ■ High Current. ■ Fatigue Free. APPLICATIONS ■ High Power Drives. ■ High Voltage Power Supplies. ■ DC Motor Control.

User Programmable Laser Engine Pixel Clock Generator

Description The ICS1574B is a very high performance monolithic phase locked loop (PLL) frequency synthesizer designed for laser engine applications. Utilizing ICS’s advanced CMOS mixed mode technology, the ICS1574B provides a low cost solution for high-end pixel clock generation for a variety of

User Programmable Laser Engine Pixel Clock Generator

Description The ICS1574B is a very high performance monolithic phase locked loop (PLL) frequency synthesizer designed for laser engine applications. Utilizing ICS’s advanced CMOS mixed mode technology, the ICS1574B provides a low cost solution for high-end pixel clock generation for a variety of

Integrated FM tuner for radio receivers

GENERAL DESCRIPTION The TDA1574 is a monolithic integrated FM tuner circuit designed for use in the r.f./i.f. section of car radios and home-receivers. The circuit comprises a mixer, oscillator and a linear i.f. amplifier for signal processing, plus the following additional features. Featu

Integrated FM tuner for radio receivers

GENERAL DESCRIPTION The TDA1574T is an integrated FM tuner circuit designed for use in the RF/IF section of car radios and home receivers. The circuit contains a mixer and an oscillator and a linear IF amplifier for signal processing. The circuit also incorporates the following features. F