Dual J-K Flip-Flop with Reset High?뭁erformance Silicon?묰ate CMOS

Dual J-K Flip-Flop with Reset High−Performance Silicon−Gate CMOS The MC74HC73A is identical in pinout to the LS73. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. Each flip−flop is negative−edge clocked and has an activ

Dual JK Flip Flop with Reset

High Performance Silicon Gate CMOS. The MC74HC73A is identical in pinout to the LS73. The device inputs are compatible with standard CMOS outputs, with pullup resistors, they are compatible with LSTTL outputs. Each flip flop is negative edge clocked and has an active low asynchronous reset. The MC74 • Output Drive Capability: 10 LSTTL Loads\n• Outputs Directly Interface to CMOS, NMOS, and TTL\n• Operating Voltage Range: 2.0 to 6.0 V\n• Low Input Current: 1.0 µA\n• High Noise Immunity Characteristic of CMOS Devices\n• In Compliance with the JEDEC Standard No. 7.0 A Requirements\n• Chip Complexit;

Dual J-K Flip-Flop with Reset

文件：91.06 Kbytes Page：7 Pages

Dual J-K Flip-Flop with Reset High?뭁erformance Silicon?묰ate CMOS

Dual J-K Flip-Flop with Reset High−Performance Silicon−Gate CMOS The MC74HC73A is identical in pinout to the LS73. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. Each flip−flop is negative−edge clocked and has an activ

Dual J-K Flip-Flop with Reset High?뭁erformance Silicon?묰ate CMOS

Dual J-K Flip-Flop with Reset High−Performance Silicon−Gate CMOS The MC74HC73A is identical in pinout to the LS73. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. Each flip−flop is negative−edge clocked and has an activ

Dual J-K Flip-Flop with Reset High?뭁erformance Silicon?묰ate CMOS

Dual J-K Flip-Flop with Reset High−Performance Silicon−Gate CMOS The MC74HC73A is identical in pinout to the LS73. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. Each flip−flop is negative−edge clocked and has an activ

Dual J-K Flip-Flop with Reset High?뭁erformance Silicon?묰ate CMOS

Dual J-K Flip-Flop with Reset High−Performance Silicon−Gate CMOS The MC74HC73A is identical in pinout to the LS73. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. Each flip−flop is negative−edge clocked and has an activ

Dual J-K Flip-Flop with Reset

文件：91.06 Kbytes Page：7 Pages

Dual J-K Flip-Flop with Reset

文件：91.06 Kbytes Page：7 Pages

Dual J-K Flip-Flop with Reset

文件：91.06 Kbytes Page：7 Pages

封装/外壳：14-SOIC（0.154"，3.90mm 宽） 功能：复位 包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：IC FF JK TYPE DUAL 1BIT 14SOIC 集成电路（IC） 触发器

封装/外壳：14-TSSOP（0.173"，4.40mm 宽） 功能：复位 包装：卷带（TR）剪切带（CT） 描述：IC FF JK TYPE DUAL 1BIT 14TSSOP 集成电路（IC） 触发器

Dual J-K Flip-Flop with Reset

文件：91.06 Kbytes Page：7 Pages

Dual J-K Flip-Flop with Reset

文件：91.06 Kbytes Page：7 Pages

Dual J-K Flip-Flop with Reset

Dual J-K Flip-Flop with Reset High–Performance Silicon–Gate CMOS The MC74HC73 is identical in pinout to the LS73. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. Each flip flop is negative–edge clocked and has an active

Dual J-K Flip-Flop with Reset

Dual J-K Flip-Flop with Reset High–Performance Silicon–Gate CMOS The MC74HC73 is identical in pinout to the LS73. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. Each flip flop is negative–edge clocked and has an active

Dual J-K Flip-Flop with Reset

Dual J-K Flip-Flop with Reset High–Performance Silicon–Gate CMOS The MC74HC73 is identical in pinout to the LS73. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. Each flip flop is negative–edge clocked and has an active

Dual JK flip-flop with reset; negative-edge trigger

General description The 74HC73 is a high-speed Si-gate CMOS device and is pin compatible with low-power Schottky TTL (LSTTL). The 74HC73 is specified in compliance with JEDEC standard no. 7A. Features Low-power dissipation Complies with JEDEC standard no. 7A ESD protection:

Dual JK flip-flop with reset; negative-edge trigger

General description The 74HC73 is a high-speed Si-gate CMOS device and is pin compatible with low-power Schottky TTL (LSTTL). The 74HC73 is specified in compliance with JEDEC standard no. 7A. Features Low-power dissipation Complies with JEDEC standard no. 7A ESD protection: