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74HC73价格
参考价格：￥0.7134
型号：74HC73D,652 品牌：NXP 备注：这里有74HC73多少钱，2026年最近7天走势，今日出价，今日竞价，74HC73批发/采购报价，74HC73行情走势销售排行榜，74HC73报价。| 型号 | 功能描述 | 生产厂家 企业 | LOGO | 操作 |
|---|---|---|---|---|
74HC73 | Dual JK flip-flop with reset; negative-edge trigger General description The 74HC73 is a high-speed Si-gate CMOS device and is pin compatible with low-power Schottky TTL (LSTTL). The 74HC73 is specified in compliance with JEDEC standard no. 7A. Features Low-power dissipation Complies with JEDEC standard no. 7A ESD protection: | PHILIPS 飞利浦 |   | |
74HC73 | Dual JK flip-flop with reset; negative-edge trigger | ETC 知名厂家 | ETC | |
74HC73 | Dual JK flip-flop with reset; negative-edge trigger 1. General description The 74HC73 is a dual negative edge triggered JK flip-flop with individual J, K, clock (nCP) and reset (nR) inputs and complementary nQ and nQ outputs. The J and K inputs must be stable one set-up time prior to the HIGH-to-LOW clock transition for predictable operation. (n | NEXPERIA 安世 | | |
Dual JK flip-flop with reset; negative-edge trigger 1. General description The 74HC73 is a dual negative edge triggered JK flip-flop with individual J, K, clock (nCP) and reset (nR) inputs and complementary nQ and nQ outputs. The J and K inputs must be stable one set-up time prior to the HIGH-to-LOW clock transition for predictable operation. (n | NEXPERIA 安世 | | ||
Dual JK flip-flop with reset; negative-edge trigger General description The 74HC73 is a high-speed Si-gate CMOS device and is pin compatible with low-power Schottky TTL (LSTTL). The 74HC73 is specified in compliance with JEDEC standard no. 7A. Features Low-power dissipation Complies with JEDEC standard no. 7A ESD protection: | PHILIPS 飞利浦 | | ||
Dual JK flip-flop with reset; negative-edge trigger | ETC 知名厂家 | ETC | | |
Dual JK flip-flop with reset; negative-edge trigger | ETC 知名厂家 | ETC | | |
Dual JK flip-flop with reset; negative-edge trigger General description The 74HC73 is a high-speed Si-gate CMOS device and is pin compatible with low-power Schottky TTL (LSTTL). The 74HC73 is specified in compliance with JEDEC standard no. 7A. Features Low-power dissipation Complies with JEDEC standard no. 7A ESD protection: | PHILIPS 飞利浦 | | ||
Dual JK flip-flop with reset; negative-edge trigger 1. General description The 74HC73-Q100 is a dual negative edge triggered JK flip-flop with individual J, K, clock (nCP) and reset (nR) inputs and complementary nQ and nQ outputs. The J and K inputs must be stable one set-up time prior to the HIGH-to-LOW clock transition for predictable operatio | NEXPERIA 安世 | | ||
Dual JK flip-flop with reset; negative-edge trigger General description The 74HC73 is a high-speed Si-gate CMOS device and is pin compatible with low-power Schottky TTL (LSTTL). The 74HC73 is specified in compliance with JEDEC standard no. 7A. Features Low-power dissipation Complies with JEDEC standard no. 7A ESD protection: | PHILIPS 飞利浦 | | ||
Dual JK flip-flop with reset; negative-edge trigger | ETC 知名厂家 | ETC | | |
Dual JK flip-flop with reset; negative-edge trigger | ETC 知名厂家 | ETC | | |
Dual JK flip-flop with reset; negative-edge trigger General description The 74HC73 is a high-speed Si-gate CMOS device and is pin compatible with low-power Schottky TTL (LSTTL). The 74HC73 is specified in compliance with JEDEC standard no. 7A. Features Low-power dissipation Complies with JEDEC standard no. 7A ESD protection: | PHILIPS 飞利浦 | | ||
Dual JK flip-flop with reset; negative-edge trigger 1. General description The 74HC73 is a dual negative edge triggered JK flip-flop with individual J, K, clock (nCP) and reset (nR) inputs and complementary nQ and nQ outputs. The J and K inputs must be stable one set-up time prior to the HIGH-to-LOW clock transition for predictable operation. (n | NEXPERIA 安世 | | ||
Dual JK flip-flop with reset; negative-edge trigger 1. General description The 74HC73-Q100 is a dual negative edge triggered JK flip-flop with individual J, K, clock (nCP) and reset (nR) inputs and complementary nQ and nQ outputs. The J and K inputs must be stable one set-up time prior to the HIGH-to-LOW clock transition for predictable operatio | NEXPERIA 安世 | | ||
封装/外壳：14-SOIC（0.154"，3.90mm 宽） 功能：复位 包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：IC FF JK TYPE DUAL 1BIT 14SO 集成电路（IC） 触发器 | ETC 知名厂家 | ETC | | |
Dual JK flip-flop with reset; negative-edge trigger | NEXPERIA 安世 | | ||
封装/外壳：14-SSOP（0.209"，5.30mm 宽） 功能：复位 包装：卷带（TR） 描述：IC FF JK TYPE DUAL 1BIT 14SSOP 集成电路（IC） 触发器 | ETC 知名厂家 | ETC | | |
Dual JK flip-flop with reset; negative-edge trigger | NEXPERIA 安世 | | ||
Dual JK flip-flop with reset; negative-edge trigger | NEXPERIA 安世 | |
74HC73产品属性
- 类型
描述
- 型号
74HC73
- 功能描述
触发器 DUAL JK F/F NEG-EDGE
- RoHS
否
- 制造商
Texas Instruments
- 电路数量
2
- 逻辑系列
SN74
- 逻辑类型
D-Type Flip-Flop
- 极性
Inverting, Non-Inverting
- 输入类型
CMOS
- 传播延迟时间
4.4 ns
- 高电平输出电流
- 16 mA
- 低电平输出电流
16 mA
- 电源电压-最大
5.5 V
- 最大工作温度
+ 85 C
- 安装风格
SMD/SMT
- 封装/箱体
X2SON-8
- 封装
Reel
| IC供应商 | 芯片型号 | 品牌 | 批号 | 封装 | 库存 | 备注 | 价格 |
|---|---|---|---|---|---|---|---|
ST |
2511 |
SOP14 |
16900 |
电子元器件采购降本30%!原厂直采,砍掉中间差价 |
|||
ST/意法 |
25+ |
NA |
3 |
全新原装正品支持含税 |
|||
MOT |
24+ |
DIP |
3000 |
只做原装正品现货 欢迎来电查询15919825718 |
|||
TI |
23+24 |
9860 |
原厂原包装。终端BOM表可配单。可开13%增值税 |
||||
PHI |
18+ |
SOP3.9MM |
85600 |
保证进口原装可开17%增值税发票 |
|||
NEXPERIA/安世 |
2025+ |
SOP |
5000 |
原装进口价格优 请找坤融电子! |
|||
恩XP |
24+ |
DIP |
36500 |
原装现货/放心购买 |
|||
MOTOROLA |
DIP |
6500 |
一级代理 原装正品假一罚十价格优势长期供货 |
||||
PHI |
02+/03+ |
NULL |
2242 |
全新原装100真实现货供应 |
|||
HAR |
26+ |
TO-220 |
86720 |
全新原装正品价格最实惠 假一赔百 |
74HC73规格书下载地址
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