74HC73价格

参考价格:¥0.7134

型号:74HC73D,652 品牌:NXP 备注:这里有74HC73多少钱,2025年最近7天走势,今日出价,今日竞价,74HC73批发/采购报价,74HC73行情走势销售排行榜,74HC73报价。
型号 功能描述 生产厂家&企业 LOGO 操作
74HC73

Dual JK flip-flop with reset; negative-edge trigger

General description The 74HC73 is a high-speed Si-gate CMOS device and is pin compatible with low-power Schottky TTL (LSTTL). The 74HC73 is specified in compliance with JEDEC standard no. 7A. Features Low-power dissipation Complies with JEDEC standard no. 7A ESD protection:

Philips

飞利浦

74HC73

Dual JK flip-flop with reset; negative-edge trigger

ETC

知名厂家

74HC73

Dual JK flip-flop with reset; negative-edge trigger

1. General description The 74HC73 is a dual negative edge triggered JK flip-flop with individual J, K, clock (nCP) and reset (nR) inputs and complementary nQ and nQ outputs. The J and K inputs must be stable one set-up time prior to the HIGH-to-LOW clock transition for predictable operation. (n

NEXPERIANexperia B.V. All rights reserved

安世安世半导体(中国)有限公司

Dual JK flip-flop with reset; negative-edge trigger

1. General description The 74HC73 is a dual negative edge triggered JK flip-flop with individual J, K, clock (nCP) and reset (nR) inputs and complementary nQ and nQ outputs. The J and K inputs must be stable one set-up time prior to the HIGH-to-LOW clock transition for predictable operation. (n

NEXPERIANexperia B.V. All rights reserved

安世安世半导体(中国)有限公司

Dual JK flip-flop with reset; negative-edge trigger

General description The 74HC73 is a high-speed Si-gate CMOS device and is pin compatible with low-power Schottky TTL (LSTTL). The 74HC73 is specified in compliance with JEDEC standard no. 7A. Features Low-power dissipation Complies with JEDEC standard no. 7A ESD protection:

Philips

飞利浦

Dual JK flip-flop with reset; negative-edge trigger

ETC

知名厂家

Dual JK flip-flop with reset; negative-edge trigger

ETC

知名厂家

Dual JK flip-flop with reset; negative-edge trigger

General description The 74HC73 is a high-speed Si-gate CMOS device and is pin compatible with low-power Schottky TTL (LSTTL). The 74HC73 is specified in compliance with JEDEC standard no. 7A. Features Low-power dissipation Complies with JEDEC standard no. 7A ESD protection:

Philips

飞利浦

Dual JK flip-flop with reset; negative-edge trigger

1. General description The 74HC73-Q100 is a dual negative edge triggered JK flip-flop with individual J, K, clock (nCP) and reset (nR) inputs and complementary nQ and nQ outputs. The J and K inputs must be stable one set-up time prior to the HIGH-to-LOW clock transition for predictable operatio

NEXPERIANexperia B.V. All rights reserved

安世安世半导体(中国)有限公司

Dual JK flip-flop with reset; negative-edge trigger

General description The 74HC73 is a high-speed Si-gate CMOS device and is pin compatible with low-power Schottky TTL (LSTTL). The 74HC73 is specified in compliance with JEDEC standard no. 7A. Features Low-power dissipation Complies with JEDEC standard no. 7A ESD protection:

Philips

飞利浦

Dual JK flip-flop with reset; negative-edge trigger

ETC

知名厂家

Dual JK flip-flop with reset; negative-edge trigger

ETC

知名厂家

Dual JK flip-flop with reset; negative-edge trigger

General description The 74HC73 is a high-speed Si-gate CMOS device and is pin compatible with low-power Schottky TTL (LSTTL). The 74HC73 is specified in compliance with JEDEC standard no. 7A. Features Low-power dissipation Complies with JEDEC standard no. 7A ESD protection:

Philips

飞利浦

Dual JK flip-flop with reset; negative-edge trigger

1. General description The 74HC73 is a dual negative edge triggered JK flip-flop with individual J, K, clock (nCP) and reset (nR) inputs and complementary nQ and nQ outputs. The J and K inputs must be stable one set-up time prior to the HIGH-to-LOW clock transition for predictable operation. (n

NEXPERIANexperia B.V. All rights reserved

安世安世半导体(中国)有限公司

Dual JK flip-flop with reset; negative-edge trigger

1. General description The 74HC73-Q100 is a dual negative edge triggered JK flip-flop with individual J, K, clock (nCP) and reset (nR) inputs and complementary nQ and nQ outputs. The J and K inputs must be stable one set-up time prior to the HIGH-to-LOW clock transition for predictable operatio

NEXPERIANexperia B.V. All rights reserved

安世安世半导体(中国)有限公司

封装/外壳:14-SOIC(0.154",3.90mm 宽) 功能:复位 包装:卷带(TR)剪切带(CT)Digi-Reel® 得捷定制卷带 描述:IC FF JK TYPE DUAL 1BIT 14SO 集成电路(IC) 触发器

ETC

知名厂家

封装/外壳:14-SSOP(0.209",5.30mm 宽) 功能:复位 包装:卷带(TR) 描述:IC FF JK TYPE DUAL 1BIT 14SSOP 集成电路(IC) 触发器

ETC

知名厂家

74HC73产品属性

  • 类型

    描述

  • 型号

    74HC73

  • 功能描述

    触发器 DUAL JK F/F NEG-EDGE

  • RoHS

  • 制造商

    Texas Instruments

  • 电路数量

    2

  • 逻辑系列

    SN74

  • 逻辑类型

    D-Type Flip-Flop

  • 极性

    Inverting, Non-Inverting

  • 输入类型

    CMOS

  • 传播延迟时间

    4.4 ns

  • 高电平输出电流

    - 16 mA

  • 低电平输出电流

    16 mA

  • 电源电压-最大

    5.5 V

  • 最大工作温度

    + 85 C

  • 安装风格

    SMD/SMT

  • 封装/箱体

    X2SON-8

  • 封装

    Reel

更新时间:2025-8-10 15:01:00
IC供应商 芯片型号 品牌 批号 封装 库存 备注 价格
PHI
2447
DIP
100500
一级代理专营品牌!原装正品,优势现货,长期排单到货
原装原厂品牌
2023+
原厂封装
8700
原装现货
恩XP
23+
null
7000
NEXPERIA
2319
con
987
现货常备产品原装可到京北通宇商城查价格
恩XP
24+
N/A
16000
原装正品现货支持实单
Nexperia/安世
22+
SOT108-1
57000
原厂原装正品现货
NEXPERIA/安世
21+
SO-14
80000
只做原装,一定有货,不止网上数量,量多可订货!
PHSSEMICONDUCTOR
24+
NA
80000
只做自己库存 全新原装进口正品假一赔百 可开13%增
NEXPERIA/安世
25+
SOT402-1
600000
NEXPERIA/安世全新特价74HC73PW即刻询购立享优惠#长期有排单订
恩XP
21+
6000
只做原装正品,卖元器件不赚钱交个朋友

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