74HC73价格

参考价格:¥0.7134

型号:74HC73D,652 品牌:NXP 备注:这里有74HC73多少钱,2025年最近7天走势,今日出价,今日竞价,74HC73批发/采购报价,74HC73行情走势销售排行榜,74HC73报价。
型号 功能描述 生产厂家&企业 LOGO 操作
74HC73

Dual JK flip-flop with reset; negative-edge trigger

General description The 74HC73 is a high-speed Si-gate CMOS device and is pin compatible with low-power Schottky TTL (LSTTL). The 74HC73 is specified in compliance with JEDEC standard no. 7A. Features Low-power dissipation Complies with JEDEC standard no. 7A ESD protection:

Philips

飞利浦

74HC73

Dual JK flip-flop with reset; negative-edge trigger

ETC

知名厂家

74HC73

Dual JK flip-flop with reset; negative-edge trigger

1. General description The 74HC73 is a dual negative edge triggered JK flip-flop with individual J, K, clock (nCP) and reset (nR) inputs and complementary nQ and nQ outputs. The J and K inputs must be stable one set-up time prior to the HIGH-to-LOW clock transition for predictable operation. (n

NEXPERIANexperia B.V. All rights reserved

安世安世半导体(中国)有限公司

Dual JK flip-flop with reset; negative-edge trigger

1. General description The 74HC73 is a dual negative edge triggered JK flip-flop with individual J, K, clock (nCP) and reset (nR) inputs and complementary nQ and nQ outputs. The J and K inputs must be stable one set-up time prior to the HIGH-to-LOW clock transition for predictable operation. (n

NEXPERIANexperia B.V. All rights reserved

安世安世半导体(中国)有限公司

Dual JK flip-flop with reset; negative-edge trigger

General description The 74HC73 is a high-speed Si-gate CMOS device and is pin compatible with low-power Schottky TTL (LSTTL). The 74HC73 is specified in compliance with JEDEC standard no. 7A. Features Low-power dissipation Complies with JEDEC standard no. 7A ESD protection:

Philips

飞利浦

Dual JK flip-flop with reset; negative-edge trigger

ETC

知名厂家

Dual JK flip-flop with reset; negative-edge trigger

ETC

知名厂家

Dual JK flip-flop with reset; negative-edge trigger

General description The 74HC73 is a high-speed Si-gate CMOS device and is pin compatible with low-power Schottky TTL (LSTTL). The 74HC73 is specified in compliance with JEDEC standard no. 7A. Features Low-power dissipation Complies with JEDEC standard no. 7A ESD protection:

Philips

飞利浦

Dual JK flip-flop with reset; negative-edge trigger

1. General description The 74HC73-Q100 is a dual negative edge triggered JK flip-flop with individual J, K, clock (nCP) and reset (nR) inputs and complementary nQ and nQ outputs. The J and K inputs must be stable one set-up time prior to the HIGH-to-LOW clock transition for predictable operatio

NEXPERIANexperia B.V. All rights reserved

安世安世半导体(中国)有限公司

Dual JK flip-flop with reset; negative-edge trigger

General description The 74HC73 is a high-speed Si-gate CMOS device and is pin compatible with low-power Schottky TTL (LSTTL). The 74HC73 is specified in compliance with JEDEC standard no. 7A. Features Low-power dissipation Complies with JEDEC standard no. 7A ESD protection:

Philips

飞利浦

Dual JK flip-flop with reset; negative-edge trigger

ETC

知名厂家

Dual JK flip-flop with reset; negative-edge trigger

ETC

知名厂家

Dual JK flip-flop with reset; negative-edge trigger

General description The 74HC73 is a high-speed Si-gate CMOS device and is pin compatible with low-power Schottky TTL (LSTTL). The 74HC73 is specified in compliance with JEDEC standard no. 7A. Features Low-power dissipation Complies with JEDEC standard no. 7A ESD protection:

Philips

飞利浦

Dual JK flip-flop with reset; negative-edge trigger

1. General description The 74HC73 is a dual negative edge triggered JK flip-flop with individual J, K, clock (nCP) and reset (nR) inputs and complementary nQ and nQ outputs. The J and K inputs must be stable one set-up time prior to the HIGH-to-LOW clock transition for predictable operation. (n

NEXPERIANexperia B.V. All rights reserved

安世安世半导体(中国)有限公司

Dual JK flip-flop with reset; negative-edge trigger

1. General description The 74HC73-Q100 is a dual negative edge triggered JK flip-flop with individual J, K, clock (nCP) and reset (nR) inputs and complementary nQ and nQ outputs. The J and K inputs must be stable one set-up time prior to the HIGH-to-LOW clock transition for predictable operatio

NEXPERIANexperia B.V. All rights reserved

安世安世半导体(中国)有限公司

封装/外壳:14-SOIC(0.154",3.90mm 宽) 功能:复位 包装:卷带(TR)剪切带(CT)Digi-Reel® 得捷定制卷带 描述:IC FF JK TYPE DUAL 1BIT 14SO 集成电路(IC) 触发器

ETC

知名厂家

封装/外壳:14-SSOP(0.209",5.30mm 宽) 功能:复位 包装:卷带(TR) 描述:IC FF JK TYPE DUAL 1BIT 14SSOP 集成电路(IC) 触发器

ETC

知名厂家

74HC73产品属性

  • 类型

    描述

  • 型号

    74HC73

  • 功能描述

    触发器 DUAL JK F/F NEG-EDGE

  • RoHS

  • 制造商

    Texas Instruments

  • 电路数量

    2

  • 逻辑系列

    SN74

  • 逻辑类型

    D-Type Flip-Flop

  • 极性

    Inverting, Non-Inverting

  • 输入类型

    CMOS

  • 传播延迟时间

    4.4 ns

  • 高电平输出电流

    - 16 mA

  • 低电平输出电流

    16 mA

  • 电源电压-最大

    5.5 V

  • 最大工作温度

    + 85 C

  • 安装风格

    SMD/SMT

  • 封装/箱体

    X2SON-8

  • 封装

    Reel

更新时间:2025-8-10 20:00:00
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恩XP
23+
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2024
DIP14
13500
16余年资质 绝对原盒原盘代理渠道 更多数量
恩XP
22+
SOP-14
8000
原装正品支持实单
恩XP
25+
SOP14
3000
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TSSOP48
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22+
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57000
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23+
14-TSSOP
6500
原装正品 正规报关 可开增值税票

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