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74HC73价格

参考价格:¥0.7134

型号:74HC73D,652 品牌:NXP 备注:这里有74HC73多少钱,2026年最近7天走势,今日出价,今日竞价,74HC73批发/采购报价,74HC73行情走势销售排行榜,74HC73报价。
型号 功能描述 生产厂家 企业 LOGO 操作
74HC73

Dual JK flip-flop with reset; negative-edge trigger

General description The 74HC73 is a high-speed Si-gate CMOS device and is pin compatible with low-power Schottky TTL (LSTTL). The 74HC73 is specified in compliance with JEDEC standard no. 7A. Features Low-power dissipation Complies with JEDEC standard no. 7A ESD protection:

PHILIPS

飞利浦

74HC73

Dual JK flip-flop with reset; negative-edge trigger

ETC

知名厂家

74HC73

Dual JK flip-flop with reset; negative-edge trigger

1. General description The 74HC73 is a dual negative edge triggered JK flip-flop with individual J, K, clock (nCP) and reset (nR) inputs and complementary nQ and nQ outputs. The J and K inputs must be stable one set-up time prior to the HIGH-to-LOW clock transition for predictable operation. (n

NEXPERIA

安世

Dual JK flip-flop with reset; negative-edge trigger

1. General description The 74HC73 is a dual negative edge triggered JK flip-flop with individual J, K, clock (nCP) and reset (nR) inputs and complementary nQ and nQ outputs. The J and K inputs must be stable one set-up time prior to the HIGH-to-LOW clock transition for predictable operation. (n

NEXPERIA

安世

Dual JK flip-flop with reset; negative-edge trigger

ETC

知名厂家

Dual JK flip-flop with reset; negative-edge trigger

General description The 74HC73 is a high-speed Si-gate CMOS device and is pin compatible with low-power Schottky TTL (LSTTL). The 74HC73 is specified in compliance with JEDEC standard no. 7A. Features Low-power dissipation Complies with JEDEC standard no. 7A ESD protection:

PHILIPS

飞利浦

Dual JK flip-flop with reset; negative-edge trigger

General description The 74HC73 is a high-speed Si-gate CMOS device and is pin compatible with low-power Schottky TTL (LSTTL). The 74HC73 is specified in compliance with JEDEC standard no. 7A. Features Low-power dissipation Complies with JEDEC standard no. 7A ESD protection:

PHILIPS

飞利浦

Dual JK flip-flop with reset; negative-edge trigger

ETC

知名厂家

Dual JK flip-flop with reset; negative-edge trigger

The 74HC73 is a dual negative edge triggered JK flip-flop with individual J, K, clock (nCP) and reset (nR) inputs and complementary nQ and nQ outputs. The J and K inputs must be stable one set-up time prior to the HIGH-to-LOW clock transition for predictable operation. (nR) is asynchronous, when LOW • Low-power dissipation\n• Complies with JEDEC standard no. 7A\n• ESD protection:• HBM JESD22-A114F exceeds 2000 V\n• MM JESD22-A115-A exceeds 200 V\n\n• Multiple package options\n• Specified from -40 °C to +80 °C and from -40 °C to +125 °C;

NEXPERIA

安世

Dual JK flip-flop with reset; negative-edge trigger

The 74HC73-Q100 is a dual negative edge triggered JK flip-flop with individual J, K, clock (nCP) and reset (nR) inputs and complementary nQ and nQ outputs. The J and K inputs must be stable one set-up time prior to the HIGH-to-LOW clock transition for predictable operation. (nR) is asynchronous, whe • Automotive product qualification in accordance with AEC-Q100 (Grade 1)• Specified from -40 °C to +85 °C and from -40 °C to +125 °C\n\n• CMOS low-power dissipation\n• Wide supply voltage range from 2.0 to 6.0 V\n• High noise immunity\n• Latch-up performance exceeds 100 mA per JESD 78 Class II Level;

NEXPERIA

安世

Dual JK flip-flop with reset; negative-edge trigger

1. General description The 74HC73-Q100 is a dual negative edge triggered JK flip-flop with individual J, K, clock (nCP) and reset (nR) inputs and complementary nQ and nQ outputs. The J and K inputs must be stable one set-up time prior to the HIGH-to-LOW clock transition for predictable operatio

NEXPERIA

安世

Dual JK flip-flop with reset; negative-edge trigger

ETC

知名厂家

Dual JK flip-flop with reset; negative-edge trigger

General description The 74HC73 is a high-speed Si-gate CMOS device and is pin compatible with low-power Schottky TTL (LSTTL). The 74HC73 is specified in compliance with JEDEC standard no. 7A. Features Low-power dissipation Complies with JEDEC standard no. 7A ESD protection:

PHILIPS

飞利浦

Dual JK flip-flop with reset; negative-edge trigger

General description The 74HC73 is a high-speed Si-gate CMOS device and is pin compatible with low-power Schottky TTL (LSTTL). The 74HC73 is specified in compliance with JEDEC standard no. 7A. Features Low-power dissipation Complies with JEDEC standard no. 7A ESD protection:

PHILIPS

飞利浦

Dual JK flip-flop with reset; negative-edge trigger

ETC

知名厂家

Dual JK flip-flop with reset; negative-edge trigger

1. General description The 74HC73 is a dual negative edge triggered JK flip-flop with individual J, K, clock (nCP) and reset (nR) inputs and complementary nQ and nQ outputs. The J and K inputs must be stable one set-up time prior to the HIGH-to-LOW clock transition for predictable operation. (n

NEXPERIA

安世

Dual JK flip-flop with reset; negative-edge trigger

The 74HC73 is a dual negative edge triggered JK flip-flop with individual J, K, clock (nCP) and reset (nR) inputs and complementary nQ and nQ outputs. The J and K inputs must be stable one set-up time prior to the HIGH-to-LOW clock transition for predictable operation. (nR) is asynchronous, when LOW • Low-power dissipation\n• Complies with JEDEC standard no. 7A\n• ESD protection:• HBM JESD22-A114F exceeds 2000 V\n• MM JESD22-A115-A exceeds 200 V\n\n• Multiple package options\n• Specified from -40 °C to +80 °C and from -40 °C to +125 °C;

NEXPERIA

安世

Dual JK flip-flop with reset; negative-edge trigger

1. General description The 74HC73-Q100 is a dual negative edge triggered JK flip-flop with individual J, K, clock (nCP) and reset (nR) inputs and complementary nQ and nQ outputs. The J and K inputs must be stable one set-up time prior to the HIGH-to-LOW clock transition for predictable operatio

NEXPERIA

安世

封装/外壳:14-SOIC(0.154",3.90mm 宽) 功能:复位 包装:卷带(TR)剪切带(CT)Digi-Reel® 得捷定制卷带 描述:IC FF JK TYPE DUAL 1BIT 14SO 集成电路(IC) 触发器

ETC

知名厂家

封装/外壳:14-SSOP(0.209",5.30mm 宽) 功能:复位 包装:卷带(TR) 描述:IC FF JK TYPE DUAL 1BIT 14SSOP 集成电路(IC) 触发器

ETC

知名厂家

Dual J-K Flip-Flop with Reset

Dual J-K Flip-Flop with Reset High–Performance Silicon–Gate CMOS The MC74HC73 is identical in pinout to the LS73. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. Each flip flop is negative–edge clocked and has an active

MOTOROLA

摩托罗拉

Dual J-K Flip-Flop with Reset

Dual J-K Flip-Flop with Reset High–Performance Silicon–Gate CMOS The MC74HC73 is identical in pinout to the LS73. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. Each flip flop is negative–edge clocked and has an active

MOTOROLA

摩托罗拉

Dual J-K Flip-Flop with Reset

Dual J-K Flip-Flop with Reset High–Performance Silicon–Gate CMOS The MC74HC73 is identical in pinout to the LS73. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. Each flip flop is negative–edge clocked and has an active

MOTOROLA

摩托罗拉

74HC73产品属性

  • 类型

    描述

  • VCC (V):

    2.0 - 6.0

  • Logic switching levels:

    CMOS

  • Output drive capability (mA):

    ± 5.2

  • tpd (ns):

    16

  • fmax (MHz):

    77

  • Power dissipation considerations:

    low

  • Tamb (°C):

    -40~125

  • Rth(j-a) (K/W):

    74

  • Ψth(j-top) (K/W):

    1.0

  • Rth(j-c) (K/W):

    31

  • Package name:

    SO14

更新时间:2026-5-18 22:59:00
IC供应商 芯片型号 品牌 批号 封装 库存 备注 价格
恩XP
24+
标准封装
46248
全新原装正品/价格优惠/质量保障
NEXPERIA/安世
25+
SOT402-1
600000
NEXPERIA/安世全新特价74HC73PW即刻询购立享优惠#长期有排单订
NEXPERIA/安世
20+
167
只做原装真实库存13714450367
NEXPERIA/安世
2025+
SOP
5000
原装进口价格优 请找坤融电子!
恩XP
23+
N/A
12000
一级代理,专注军工、汽车、医疗、工业、新能源、电力
恩XP
24+
SOP14
9100
绝对原装现货,价格低,欢迎询购!
恩XP
2025+
N/A
70000
柒号只做原装 现货价秒杀全网
恩XP
1211+
SOP14
7474
优势库存L欢迎来电咨询

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