DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP

The MC74F112 contains two independent, high-speed JK flip-flops with Direct Set and Clear inputs. Synchronous state changes are initiated by the falling edge of the clock. Triggering occurs at a voltage level of the clock and is not directly related to the transition time. The J and K inputs can c

DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP

The MC74F112 contains two independent, high-speed JK flip-flops with Direct Set and Clear inputs. Synchronous state changes are initiated by the falling edge of the clock. Triggering occurs at a voltage level of the clock and is not directly related to the transition time. The J and K inputs can c

DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP

The MC74F112 contains two independent, high-speed JK flip-flops with Direct Set and Clear inputs. Synchronous state changes are initiated by the falling edge of the clock. Triggering occurs at a voltage level of the clock and is not directly related to the transition time. The J and K inputs can c

DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP

The MC74F112 contains two independent, high-speed JK flip-flops with Direct Set and Clear inputs. Synchronous state changes are initiated by the falling edge of the clock. Triggering occurs at a voltage level of the clock and is not directly related to the transition time. The J and K inputs can c

DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP

Triple 3-Input AND Gate

General Description This device contains three independent gates, each of which performs the logic AND function.

Triple 3-input NAND gate

74F10 Triple 3-input NAND gate 74F11 Triple 3-input AND gate

Triple 3-Input AND Gate

文件：64.269 Kbytes Page：5 Pages

Triple 3-Input AND Gate

文件：64.269 Kbytes Page：5 Pages

Triple 3-Input AND Gate

文件：96.08 Kbytes Page：8 Pages