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MC74AC10价格

参考价格:¥0.7713

型号:MC74AC10DR2G 品牌:ON 备注:这里有MC74AC10多少钱,2026年最近7天走势,今日出价,今日竞价,MC74AC10批发/采购报价,MC74AC10行情走势销售排行榜,MC74AC10报价。
型号 功能描述 生产厂家 企业 LOGO 操作
MC74AC10

TRIPLE 3-INPUT NAND GATE

Features • Outputs Source/Sink 24 mA • ′ACT10 Has TTL Compatible Inputs • Pb−Free Packages are Available

ONSEMI

安森美半导体

MC74AC10

Triple 3-Input NAND Gate

文件:87.56 Kbytes Page:8 Pages

ONSEMI

安森美半导体

MC74AC10

Triple 3-Input NAND Gate

ONSEMI

安森美半导体

Dual JK Positive Edge-Triggered Flip-Flop

Features ■ ICC reduced by 50% ■ Outputs source/sink 24mA ■ ACT109 has TTL-compatible inputs General Description The AC/ACT109 consists of two high-speed completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock wav

ONSEMI

安森美半导体

Dual JK Positive Edge?뭈riggered Flip?묯lop

The MC74AC109/74ACT109 consists of two high−speed completely independent transition clocked JK flip−flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D flip−flop (refer to MC74AC74/74ACT74 data sheet) by connecting the J

ONSEMI

安森美半导体

Dual JK Positive Edge-Triggered Flip-Flop

Features ■ ICC reduced by 50% ■ Outputs source/sink 24mA ■ ACT109 has TTL-compatible inputs General Description The AC/ACT109 consists of two high-speed completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock wav

ONSEMI

安森美半导体

Dual JK Positive Edge?뭈riggered Flip?묯lop

The MC74AC109/74ACT109 consists of two high−speed completely independent transition clocked JK flip−flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D flip−flop (refer to MC74AC74/74ACT74 data sheet) by connecting the J

ONSEMI

安森美半导体

Dual JK Positive Edge?뭈riggered Flip?묯lop

The MC74AC109/74ACT109 consists of two high−speed completely independent transition clocked JK flip−flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D flip−flop (refer to MC74AC74/74ACT74 data sheet) by connecting the J

ONSEMI

安森美半导体

Dual JK Positive Edge?뭈riggered Flip?묯lop

The MC74AC109/74ACT109 consists of two high−speed completely independent transition clocked JK flip−flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D flip−flop (refer to MC74AC74/74ACT74 data sheet) by connecting the J

ONSEMI

安森美半导体

Dual JK Positive Edge?뭈riggered Flip?묯lop

The MC74AC109/74ACT109 consists of two high−speed completely independent transition clocked JK flip−flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D flip−flop (refer to MC74AC74/74ACT74 data sheet) by connecting the J

ONSEMI

安森美半导体

Dual JK Positive Edge?뭈riggered Flip?묯lop

The MC74AC109/74ACT109 consists of two high−speed completely independent transition clocked JK flip−flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D flip−flop (refer to MC74AC74/74ACT74 data sheet) by connecting the J

ONSEMI

安森美半导体

Dual JK Positive Edge?뭈riggered Flip?묯lop

The MC74AC109/74ACT109 consists of two high−speed completely independent transition clocked JK flip−flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D flip−flop (refer to MC74AC74/74ACT74 data sheet) by connecting the J

ONSEMI

安森美半导体

Dual JK Positive Edge?뭈riggered Flip?묯lop

The MC74AC109/74ACT109 consists of two high−speed completely independent transition clocked JK flip−flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D flip−flop (refer to MC74AC74/74ACT74 data sheet) by connecting the J

ONSEMI

安森美半导体

TRIPLE 3-INPUT NAND GATE

Features • Outputs Source/Sink 24 mA • ′ACT10 Has TTL Compatible Inputs • Pb−Free Packages are Available

ONSEMI

安森美半导体

TRIPLE 3-INPUT NAND GATE

Features • Outputs Source/Sink 24 mA • ′ACT10 Has TTL Compatible Inputs • Pb−Free Packages are Available

ONSEMI

安森美半导体

Triple 3-Input NAND Gate

文件:87.56 Kbytes Page:8 Pages

ONSEMI

安森美半导体

Triple 3-Input NAND Gate

文件:87.56 Kbytes Page:8 Pages

ONSEMI

安森美半导体

封装/外壳:14-SOIC(0.154",3.90mm 宽) 包装:卷带(TR)剪切带(CT)Digi-Reel® 得捷定制卷带 描述:IC GATE NAND 3CH 3-INP 14SOIC 集成电路(IC) 门和反相器

ONSEMI

安森美半导体

封装/外壳:14-SOIC(0.154",3.90mm 宽) 包装:卷带(TR)剪切带(CT)Digi-Reel® 得捷定制卷带 描述:IC GATE NAND 3CH 3-INP 14SOIC 集成电路(IC) 门和反相器

ONSEMI

安森美半导体

Triple 3-Input NAND Gate

文件:87.56 Kbytes Page:8 Pages

ONSEMI

安森美半导体

TRIPLE 3-INPUT NAND GATE

DESCRIPTION The 74AC10 is an advanced high-speed CMOS TRIPLE 3-INPUT NAND GATE fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS tecnology. The internal circuit is composed of 3 stages including buffer output, which enables high noise immunity and stable output. All in

STMICROELECTRONICS

意法半导体

TRIPLE 3-INPUT NAND GATE

DESCRIPTION The 74AC10 is an advanced high-speed CMOS TRIPLE 3-INPUT NAND GATE fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS tecnology. The internal circuit is composed of 3 stages including buffer output, which enables high noise immunity and stable output. All in

STMICROELECTRONICS

意法半导体

MC74AC10产品属性

  • 类型

    描述

  • 型号

    MC74AC10

  • 制造商

    Motorola Inc

  • 功能描述

    Flip Flop, Dual, J/K Type, 16 Pin, Plastic, SOP

更新时间:2026-3-18 12:00:00
IC供应商 芯片型号 品牌 批号 封装 库存 备注 价格
onsemi(安森美)
2021+
SOIC-14
499
MOTOROLA/摩托罗拉
25+
DIP14
32360
MOTOROLA/摩托罗拉全新特价MC74AC10N即刻询购立享优惠#长期有货
MOTOROLAR
26+
原厂原封装
86720
全新原装正品价格最实惠 承诺假一赔百
ON/安森美
24+
TSSOP
10000
原装进口只做订货 寻找优势渠道合作
onsemi(安森美)
25+
SOP14
3238
原装现货,免费供样,技术支持,原厂对接
ON/安森美
24+
SOP14
9600
原装现货,优势供应,支持实单!
ON
23+
SOP
8650
受权代理!全新原装现货特价热卖!
ON
ROHS
56520
一级代理 原装正品假一罚十价格优势长期供货
MOTOROLAR
24+
SOP-16
25000
一级专营品牌全新原装热卖
ON/安森美
23+
TSSOP
10000
一级代理原厂VIP渠道,专注军工、汽车、医疗、工业、

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