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74AC10价格
参考价格：￥8.9817
型号：74AC10SJ 品牌：Fairchild 备注：这里有74AC10多少钱，2025年最近7天走势，今日出价，今日竞价，74AC10批发/采购报价，74AC10行情走势销售排行榜，74AC10报价。| 型号 | 功能描述 | 生产厂家 企业 | LOGO | 操作 |
|---|---|---|---|---|
74AC10 | TRIPLE 3-INPUT NAND GATE DESCRIPTION The 74AC10 is an advanced high-speed CMOS TRIPLE 3-INPUT NAND GATE fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS tecnology. The internal circuit is composed of 3 stages including buffer output, which enables high noise immunity and stable output. All in | STMICROELECTRONICS 意法半导体 |   | |
74AC10 | Triple 3-Input NAND Gate General Description The AC/ACT10 contains three, 3-input NAND gates. Features ■ ICC reduced by 50 on 74AC only ■ Outputs source/sink 24mA | Fairchild 仙童半导体 | | |
74AC10 | TRIPLE 3-INPUT NAND GATE 文件：182.7 Kbytes Page：8 Pages | STMICROELECTRONICS 意法半导体 | | |
74AC10 | Triple 3-Input NAND Gate 文件：102.64 Kbytes Page：7 Pages | Fairchild 仙童半导体 | | |
74AC10 | TRIPLE 3-INPUT NAND GATE | STMICROELECTRONICS 意法半导体 | | |
74AC10 | Triple 3-Input NAND Gate | ONSEMI 安森美半导体 | | |
Dual JK Positive Edge-Triggered Flip-Flop General Description The AC/ACT109 consists of two high-speed completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D-Type flip-flop (refer to AC/ACT74 data sheet) by connecti | Fairchild 仙童半导体 | | ||
Dual JK Positive Edge?뭈riggered Flip?묯lop The MC74AC109/74ACT109 consists of two high−speed completely independent transition clocked JK flip−flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D flip−flop (refer to MC74AC74/74ACT74 data sheet) by connecting the J | ONSEMI 安森美半导体 | | ||
Dual JK Positive Edge-Triggered Flip-Flop General Description The AC/ACT109 consists of two high-speed completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D-Type flip-flop (refer to AC/ACT74 data sheet) by connecti | Fairchild 仙童半导体 | | ||
Dual JK Positive Edge-Triggered Flip-Flop Features ■ ICC reduced by 50% ■ Outputs source/sink 24mA ■ ACT109 has TTL-compatible inputs General Description The AC/ACT109 consists of two high-speed completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock wav | ONSEMI 安森美半导体 | | ||
Dual JK Positive Edge-Triggered Flip-Flop General Description The AC/ACT109 consists of two high-speed completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D-Type flip-flop (refer to AC/ACT74 data sheet) by connecti | Fairchild 仙童半导体 | | ||
Dual JK Positive Edge-Triggered Flip-Flop General Description The AC/ACT109 consists of two high-speed completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D-Type flip-flop (refer to AC/ACT74 data sheet) by connecti | Fairchild 仙童半导体 | | ||
Dual JK Positive Edge-Triggered Flip-Flop Features ■ ICC reduced by 50% ■ Outputs source/sink 24mA ■ ACT109 has TTL-compatible inputs General Description The AC/ACT109 consists of two high-speed completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock wav | ONSEMI 安森美半导体 | | ||
Dual JK Positive Edge-Triggered Flip-Flop Features ■ ICC reduced by 50% ■ Outputs source/sink 24mA ■ ACT109 has TTL-compatible inputs General Description The AC/ACT109 consists of two high-speed completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock wav | ONSEMI 安森美半导体 | | ||
Dual JK Positive Edge-Triggered Flip-Flop General Description The AC/ACT109 consists of two high-speed completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D-Type flip-flop (refer to AC/ACT74 data sheet) by connecti | Fairchild 仙童半导体 | | ||
TRIPLE 3-INPUT NAND GATE DESCRIPTION The 74AC10 is an advanced high-speed CMOS TRIPLE 3-INPUT NAND GATE fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS tecnology. The internal circuit is composed of 3 stages including buffer output, which enables high noise immunity and stable output. All in | STMICROELECTRONICS 意法半导体 | | ||
TRIPLE 3-INPUT NAND GATE DESCRIPTION The 74AC10 is an advanced high-speed CMOS TRIPLE 3-INPUT NAND GATE fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS tecnology. The internal circuit is composed of 3 stages including buffer output, which enables high noise immunity and stable output. All in | STMICROELECTRONICS 意法半导体 | | ||
Triple 3-Input NAND Gate General Description The AC/ACT10 contains three, 3-input NAND gates. Features ■ ICC reduced by 50 on 74AC only ■ Outputs source/sink 24mA | Fairchild 仙童半导体 | | ||
Triple 3-Input NAND Gate General Description The AC/ACT10 contains three, 3-input NAND gates. Features ■ ICC reduced by 50 on 74AC only ■ Outputs source/sink 24mA | Fairchild 仙童半导体 | | ||
Triple 3-Input NAND Gate General Description The AC/ACT10 contains three, 3-input NAND gates. Features ■ ICC reduced by 50 on 74AC only ■ Outputs source/sink 24mA | Fairchild 仙童半导体 | | ||
Triple 3-Input NAND Gate General Description The AC/ACT10 contains three, 3-input NAND gates. Features ■ ICC reduced by 50 on 74AC only ■ Outputs source/sink 24mA | Fairchild 仙童半导体 | | ||
TRIPLE 3-INPUT NAND GATE 文件：182.7 Kbytes Page：8 Pages | STMICROELECTRONICS 意法半导体 | | ||
Dual JK Positive Edge−Triggered Flip−Flop | ONSEMI 安森美半导体 | | ||
Dual JK Positive Edge-Triggered Flip-Flop 文件：339.62 Kbytes Page：12 Pages | Fairchild 仙童半导体 | | ||
Dual JK Positive Edge-Triggered Flip-Flop 文件：339.62 Kbytes Page：12 Pages | Fairchild 仙童半导体 | | ||
Dual JK Positive Edge-Triggered Flip-Flop 文件：339.62 Kbytes Page：12 Pages | Fairchild 仙童半导体 | | ||
封装/外壳：16-TSSOP（0.173"，4.40mm 宽） 功能：设置（预设）和复位 包装：管件 描述：IC FF JK TYPE DUAL 1BIT 16TSSOP 集成电路（IC） 触发器 | ONSEMI 安森美半导体 | | ||
封装/外壳：16-DIP（0.300"，7.62mm） 功能：设置（预设）和复位 包装：袋 描述：IC FF JK TYPE DUAL 1BIT 16DIP 集成电路（IC） 触发器 | ONSEMI 安森美半导体 | | ||
Dual JK Positive Edge-Triggered Flip-Flop 文件：339.62 Kbytes Page：12 Pages | Fairchild 仙童半导体 | | ||
Dual JK Positive Edge-Triggered Flip-Flop 文件：339.62 Kbytes Page：12 Pages | Fairchild 仙童半导体 | | ||
TRIPLE 3-INPUT NAND GATE 文件：182.7 Kbytes Page：8 Pages | STMICROELECTRONICS 意法半导体 | | ||
TRIPLE 3-INPUT NAND GATE 文件：182.7 Kbytes Page：8 Pages | STMICROELECTRONICS 意法半导体 | | ||
Triple 3-Input NAND Gate 文件：102.64 Kbytes Page：7 Pages | Fairchild 仙童半导体 | | ||
TRIPLE 3-INPUT NAND GATE 文件：182.7 Kbytes Page：8 Pages | STMICROELECTRONICS 意法半导体 | | ||
Triple 3-Input NAND Gate 文件：102.64 Kbytes Page：7 Pages | Fairchild 仙童半导体 | | ||
Triple 3-Input NAND Gate 文件：102.64 Kbytes Page：7 Pages | Fairchild 仙童半导体 | | ||
Triple 3-Input NAND Gate 文件：102.64 Kbytes Page：7 Pages | Fairchild 仙童半导体 | | ||
Triple 3-Input NAND Gate 文件：102.64 Kbytes Page：7 Pages | Fairchild 仙童半导体 | | ||
TRIPLE 3-INPUT NAND GATE 文件：182.7 Kbytes Page：8 Pages | STMICROELECTRONICS 意法半导体 | |
74AC10产品属性
- 类型
描述
- 型号
74AC10
- 制造商
FAIRCHILD
- 制造商全称
Fairchild Semiconductor
- 功能描述
Triple 3-Input NAND Gate
| IC供应商 | 芯片型号 | 品牌 | 批号 | 封装 | 库存 | 备注 | 价格 |
|---|---|---|---|---|---|---|---|
FAI |
22+ |
SOP |
1000 |
全新原装现货!自家库存! |
|||
ON |
2023+ |
SOP-14 |
50000 |
原装现货 |
|||
MOT |
25+23+ |
SOP |
47021 |
绝对原装正品现货,全新深圳原装进口现货 |
|||
ON/安森美 |
18+ |
SOP-16 |
12500 |
全新原装正品,本司专业配单,大单小单都配 |
|||
FAIRCHILD |
23+ |
SMD-SO14 |
9856 |
原装正品,假一罚百! |
|||
HAR |
23+ |
DIP-16 |
6800 |
只做原装正品假一赔十为客户做到零风险!! |
|||
NS |
23+ |
SOP8 |
66600 |
专业芯片配单原装正品假一罚十 |
|||
FAI |
24+ |
SMD |
20000 |
一级代理原装现货假一罚十 |
|||
FAIRCHILD/仙童 |
9900 |
SOP14 |
395 |
原装现货 |
|||
TI/德州仪器 |
25+ |
DIP16 |
32360 |
TI/德州仪器全新特价74AC109PC即刻询购立享优惠#长期有货 |
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74AC10规格书下载地址
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DdatasheetPDF页码索引
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