2.5V / 3.3V ECL 2-Input Differential AND/NAND

Description The MC100LVEP05 is a 2−input differential AND/NAND gate. The MC100LVEP05 is the low voltage version of the MC100EP05 and is functionally equivalent to the EL05 and LVEL05 devices. With AC performance much faster than the LVEL05 device, the MC100LVEP05 is ideal for low voltage applicat

2.5V / 3.3V ECL 2-Input Differential AND/NAND

Description The MC100LVEP05 is a 2−input differential AND/NAND gate. The MC100LVEP05 is the low voltage version of the MC100EP05 and is functionally equivalent to the EL05 and LVEL05 devices. With AC performance much faster than the LVEL05 device, the MC100LVEP05 is ideal for low voltage applicat

2.5V / 3.3V ECL 2-Input Differential AND/NAND

Description The MC100LVEP05 is a 2−input differential AND/NAND gate. The MC100LVEP05 is the low voltage version of the MC100EP05 and is functionally equivalent to the EL05 and LVEL05 devices. With AC performance much faster than the LVEL05 device, the MC100LVEP05 is ideal for low voltage applicat

2.5V / 3.3V ECL 2-Input Differential AND/NAND

Description The MC100LVEP05 is a 2−input differential AND/NAND gate. The MC100LVEP05 is the low voltage version of the MC100EP05 and is functionally equivalent to the EL05 and LVEL05 devices. With AC performance much faster than the LVEL05 device, the MC100LVEP05 is ideal for low voltage applicat

2.5V / 3.3V ECL 1:2 Differential Fanout Buffer

Description The MC10/100LVEP11 is a differential 1:2 fanout buffer. The device is pin and functionally equivalent to the EP11 device. With AC performance the same as the EP11 device, the LVEP11 is ideal for applications requiring lower voltage. Single−ended CLK input operation is limited to a V

Low-Voltage 1:10 Differential LVECL/LVPECL/LVEPECL/HSTL Clock Driver

Description The MC100LVEP111 is a low skew 1−to−10 differential driver, designed with clock distribution in mind, accepting two clock sources into an input multiplexer. The PECL input signals can be either differential or single−ended (if the VBB output is used). HSTL inputs can be used when th

Low-Voltage 1:10 Differential LVECL/LVPECL/LVEPECL/HSTL Clock Driver

Description The MC100LVEP111 is a low skew 1−to−10 differential driver, designed with clock distribution in mind, accepting two clock sources into an input multiplexer. The PECL input signals can be either differential or single−ended (if the VBB output is used). HSTL inputs can be used when th

Low-Voltage 1:10 Differential LVECL/LVPECL/LVEPECL/HSTL Clock Driver

Description The MC100LVEP111 is a low skew 1−to−10 differential driver, designed with clock distribution in mind, accepting two clock sources into an input multiplexer. The PECL input signals can be either differential or single−ended (if the VBB output is used). HSTL inputs can be used when th

2.5V / 3.3V ECL 1:2 Differential Fanout Buffer

Description The MC10/100LVEP11 is a differential 1:2 fanout buffer. The device is pin and functionally equivalent to the EP11 device. With AC performance the same as the EP11 device, the LVEP11 is ideal for applications requiring lower voltage. Single−ended CLK input operation is limited to a V

2.5V / 3.3V ECL 1:2 Differential Fanout Buffer

Description The MC10/100LVEP11 is a differential 1:2 fanout buffer. The device is pin and functionally equivalent to the EP11 device. With AC performance the same as the EP11 device, the LVEP11 is ideal for applications requiring lower voltage. Single−ended CLK input operation is limited to a V

2.5V / 3.3V ECL 1:2 Differential Fanout Buffer

Description The MC10/100LVEP11 is a differential 1:2 fanout buffer. The device is pin and functionally equivalent to the EP11 device. With AC performance the same as the EP11 device, the LVEP11 is ideal for applications requiring lower voltage. Single−ended CLK input operation is limited to a V

2.5V / 3.3V ECL 1:2 Differential Fanout Buffer

Description The MC10/100LVEP11 is a differential 1:2 fanout buffer. The device is pin and functionally equivalent to the EP11 device. With AC performance the same as the EP11 device, the LVEP11 is ideal for applications requiring lower voltage. Single−ended CLK input operation is limited to a V

Low-Voltage 1:5 Differential LVECL/LVPECL/LVEPECL/HSTL Clock Driver

Description The MC100LVEP14 is a low skew 1−to−5 differential driver, designed with clock distribution in mind, accepting two clock sources into an input multiplexer. The ECL/PECL input signals can be either differential or single−ended (if the VBB output is used). HSTL inputs can be used when

Low-Voltage 1:5 Differential LVECL/LVPECL/LVEPECL/HSTL Clock Driver

Description The MC100LVEP14 is a low skew 1−to−5 differential driver, designed with clock distribution in mind, accepting two clock sources into an input multiplexer. The ECL/PECL input signals can be either differential or single−ended (if the VBB output is used). HSTL inputs can be used when

Low-Voltage 1:5 Differential LVECL/LVPECL/LVEPECL/HSTL Clock Driver

Description The MC100LVEP14 is a low skew 1−to−5 differential driver, designed with clock distribution in mind, accepting two clock sources into an input multiplexer. The ECL/PECL input signals can be either differential or single−ended (if the VBB output is used). HSTL inputs can be used when

Clock Management Design Using Low Skew and Low Jitter Devices

Why Do We Need Clock Management? Can you imagine the chaos in our world if our clocks or watches were not synchronized to Greenwich Mean Time? How would trains, buses, and airplanes run on schedule? The miniseries Longitude was the story of a man who made a major technological breakthrough by inv

2.5V / 3.3V ECL Differential Receiver/Driver

Description The MC10/100LVEP16 is a world class differential receiver/driver. The device is functionally equivalent to the EL16, EP16 and LVEL16 devices. With output transition times significantly faster than the EL16 and LVEL16, the LVEP16 is ideally suited for interfacing with high frequency an

2.5V / 3.3V ECL Differential Receiver/Driver

Description The MC10/100LVEP16 is a world class differential receiver/driver. The device is functionally equivalent to the EL16, EP16 and LVEL16 devices. With output transition times significantly faster than the EL16 and LVEL16, the LVEP16 is ideally suited for interfacing with high frequency an

2.5V / 3.3V ECL Differential Receiver/Driver

Description The MC10/100LVEP16 is a world class differential receiver/driver. The device is functionally equivalent to the EL16, EP16 and LVEL16 devices. With output transition times significantly faster than the EL16 and LVEL16, the LVEP16 is ideally suited for interfacing with high frequency an

2.5V / 3.3V ECL Differential Receiver/Driver

Description The MC10/100LVEP16 is a world class differential receiver/driver. The device is functionally equivalent to the EL16, EP16 and LVEL16 devices. With output transition times significantly faster than the EL16 and LVEL16, the LVEP16 is ideally suited for interfacing with high frequency an

2.5V / 3.3V ECL Differential Receiver/Driver

Description The MC10/100LVEP16 is a world class differential receiver/driver. The device is functionally equivalent to the EL16, EP16 and LVEL16 devices. With output transition times significantly faster than the EL16 and LVEL16, the LVEP16 is ideally suited for interfacing with high frequency an

2.5V / 3.3V ECL Differential Receiver/Driver

Description The MC10/100LVEP16 is a world class differential receiver/driver. The device is functionally equivalent to the EL16, EP16 and LVEL16 devices. With output transition times significantly faster than the EL16 and LVEL16, the LVEP16 is ideally suited for interfacing with high frequency an

2.5V / 3.3V ECL Differential Receiver/Driver

Description The MC10/100LVEP16 is a world class differential receiver/driver. The device is functionally equivalent to the EL16, EP16 and LVEL16 devices. With output transition times significantly faster than the EL16 and LVEL16, the LVEP16 is ideally suited for interfacing with high frequency an

Clock Management Design Using Low Skew and Low Jitter Devices

Why Do We Need Clock Management? Can you imagine the chaos in our world if our clocks or watches were not synchronized to Greenwich Mean Time? How would trains, buses, and airplanes run on schedule? The miniseries Longitude was the story of a man who made a major technological breakthrough by inv

Low-Voltage 1:5 Dual Diff.LVECL/LVPECL/LVEPECL/HSTL Clock Driver

Description The MC100LVEP210 is a low skew 1−to−5 dual differential driver, designed with clock distribution in mind. The ECL/PECL input signals can be either differential or single−ended if the VBB output is used. The signal is fanned out to 5 identical differential outputs. HSTL inputs can be u

Low-Voltage 1:5 Dual Diff.LVECL/LVPECL/LVEPECL/HSTL Clock Driver

Description The MC100LVEP210 is a low skew 1−to−5 dual differential driver, designed with clock distribution in mind. The ECL/PECL input signals can be either differential or single−ended if the VBB output is used. The signal is fanned out to 5 identical differential outputs. HSTL inputs can be u

Low-Voltage 1:5 Dual Diff.LVECL/LVPECL/LVEPECL/HSTL Clock Driver

Description The MC100LVEP210 is a low skew 1−to−5 dual differential driver, designed with clock distribution in mind. The ECL/PECL input signals can be either differential or single−ended if the VBB output is used. The signal is fanned out to 5 identical differential outputs. HSTL inputs can be u

2.5V / 3.3V ECL /2, /4, /8 Clock Generation Chip

The MC100LVEP34 is a low skew ÷2, ÷4, ÷8 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The VBB pin, an internally generated voltage supply, is

Clock Management Design Using Low Skew and Low Jitter Devices

Why Do We Need Clock Management? Can you imagine the chaos in our world if our clocks or watches were not synchronized to Greenwich Mean Time? How would trains, buses, and airplanes run on schedule? The miniseries Longitude was the story of a man who made a major technological breakthrough by inv

2.5V / 3.3V ECL /2, /4, /8 Clock Generation Chip

The MC100LVEP34 is a low skew ÷2, ÷4, ÷8 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The VBB pin, an internally generated voltage supply, is

2.5V / 3.3V ECL /2, /4, /8 Clock Generation Chip

The MC100LVEP34 is a low skew ÷2, ÷4, ÷8 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The VBB pin, an internally generated voltage supply, is

2.5V / 3.3V ECL /2, /4, /8 Clock Generation Chip

The MC100LVEP34 is a low skew ÷2, ÷4, ÷8 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The VBB pin, an internally generated voltage supply, is

2.5V / 3.3V ECL /2, /4, /8 Clock Generation Chip

The MC100LVEP34 is a low skew ÷2, ÷4, ÷8 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The VBB pin, an internally generated voltage supply, is

2.5V / 3.3V ECL /2, /4, /8 Clock Generation Chip

The MC100LVEP34 is a low skew ÷2, ÷4, ÷8 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The VBB pin, an internally generated voltage supply, is

2.5V / 3.3V ECL 2-Input Differential AND/NAND

文件：161.66 Kbytes Page：10 Pages

2.5V / 3.3V ECL 2-Input Differential AND/NAND

文件：161.66 Kbytes Page：10 Pages

2.5V / 3.3V ECL 2-Input Differential AND/NAND

文件：161.66 Kbytes Page：10 Pages

2.5V / 3.3V ECL 2-Input Differential AND/NAND

文件：161.66 Kbytes Page：10 Pages

封装/外壳：8-SOIC（0.154"，3.90mm 宽） 包装：卷带（TR） 描述：IC GATE AND/NAND ECL 2INP 8SOIC 集成电路（IC） 门和反相器 - 多功能，可配置

封装/外壳：8-TSSOP，8-MSOP（0.118"，3.00mm 宽） 包装：管件 描述：IC GATE AND/NAND ECL 2INP 8TSSOP 集成电路（IC） 门和反相器 - 多功能，可配置

2.5V / 3.3V ECL 2-Input Differential AND/NAND

文件：161.66 Kbytes Page：10 Pages

2.5V / 3.3V ECL 2-Input Differential AND/NAND

文件：161.66 Kbytes Page：10 Pages

2.5V / 3.3V ECL 2-Input Differential AND/NAND

文件：161.66 Kbytes Page：10 Pages

ECL 1:2 差分时钟/数据扇出缓冲器

2.5V / 3.3V ECL 1:2 Differential Fanout Buffer

文件：166.19 Kbytes Page：12 Pages

2.5V / 3.3V 1:10 Differential ECL/PECL/HSTL Clock Driver

文件：155.23 Kbytes Page：10 Pages

2.5 V / 3.3 V 2:1:10 差分 ECL/PECL/HSTL 时钟/数据扇出缓冲器

2.5V / 3.3V 2:1:10 Differential ECL/PECL/HSTL Clock Driver

文件：179.08 Kbytes Page：14 Pages

2.5V / 3.3V 1:10 Differential ECL/PECL/HSTL Clock Driver

文件：155.23 Kbytes Page：10 Pages

2.5V / 3.3V 2:1:10 Differential ECL/PECL/HSTL Clock Driver

文件：179.08 Kbytes Page：14 Pages

2.5V / 3.3V 1:10 Differential ECL/PECL/HSTL Clock Driver

文件：155.23 Kbytes Page：10 Pages

2.5V / 3.3V 1:10 Differential ECL/PECL/HSTL Clock Driver

文件：155.23 Kbytes Page：10 Pages

2.5V / 3.3V 2:1:10 Differential ECL/PECL/HSTL Clock Driver

文件：179.08 Kbytes Page：14 Pages

2.5V / 3.3V 1:10 Differential ECL/PECL/HSTL Clock Driver

文件：155.23 Kbytes Page：10 Pages

2.5V / 3.3V 1:10 Differential ECL/PECL/HSTL Clock Driver

文件：155.23 Kbytes Page：10 Pages

2.5V / 3.3V 2:1:10 Differential ECL/PECL/HSTL Clock Driver

文件：179.08 Kbytes Page：14 Pages

2.5V / 3.3V 2:1:10 Differential ECL/PECL/HSTL Clock Driver

文件：179.08 Kbytes Page：14 Pages

2.5V / 3.3V 1:10 Differential ECL/PECL/HSTL Clock Driver

文件：155.23 Kbytes Page：10 Pages

2.5V / 3.3V 2:1:10 Differential ECL/PECL/HSTL Clock Driver

文件：179.08 Kbytes Page：14 Pages

2.5V / 3.3V 1:10 Differential ECL/PECL/HSTL Clock Driver

文件：155.23 Kbytes Page：10 Pages