2.5v/3.3v Differential LVPECL 1:9 Clock Distribution Buffer and Clock Driver

Features • Fully differential architecture from input to all outputs • SiGe technology supports near-zero output skew • Selectable 1:1 or 1:2 frequency outputs • LVPECL compatible differential clock inputs and outputs • LVCMOS compatible control inputs • Single 3.3V or 2.5V supply • Max. 35

2.5/3.3V Differential LVPECL 1:9 Clock Distribution Buffer and Clock Divider

文件：282.85 Kbytes Page：12 Pages

2.5v/3.3v Differential LVPECL 1:9 Clock Distribution Buffer and Clock Driver

Features • Fully differential architecture from input to all outputs • SiGe technology supports near-zero output skew • Selectable 1:1 or 1:2 frequency outputs • LVPECL compatible differential clock inputs and outputs • LVCMOS compatible control inputs • Single 3.3V or 2.5V supply • Max. 35

2.5v/3.3v Differential LVPECL 1:9 Clock Distribution Buffer and Clock Driver

Features • Fully differential architecture from input to all outputs • SiGe technology supports near-zero output skew • Selectable 1:1 or 1:2 frequency outputs • LVPECL compatible differential clock inputs and outputs • LVCMOS compatible control inputs • Single 3.3V or 2.5V supply • Max. 35

2.5/3.3V Differential LVPECL 1:9 Clock Distribution Buffer and Clock Divider

文件：282.85 Kbytes Page：12 Pages