1:2 Fanout Differential LVPECL to LVTTL Translator

Description The MC100EPT26 is a 1:2 Fanout Differential LVPECL/LVDS to LVTTL translator. Because LVPECL (Positive ECL) or LVDS levels are used only +3.3 V and ground are required. The small outline 8−lead package and the 1:2 fanout design of the EPT26 makes it ideal for applications which requi

Clock Management Design Using Low Skew and Low Jitter Devices

Why Do We Need Clock Management? Can you imagine the chaos in our world if our clocks or watches were not synchronized to Greenwich Mean Time? How would trains, buses, and airplanes run on schedule? The miniseries Longitude was the story of a man who made a major technological breakthrough by inv

3.3V 1:2 Fanout Differential LVPECL/LVDS to LVTTL Translator

文件：134.38 Kbytes Page：9 Pages

1:2 Fanout Differential LVPECL to LVTTL Translator

Description The MC100EPT26 is a 1:2 Fanout Differential LVPECL/LVDS to LVTTL translator. Because LVPECL (Positive ECL) or LVDS levels are used only +3.3 V and ground are required. The small outline 8−lead package and the 1:2 fanout design of the EPT26 makes it ideal for applications which requi

3.3V 1:2 Fanout Differential LVPECL/LVDS to LVTTL Translator

文件：134.38 Kbytes Page：9 Pages

3.3V 1:2 Fanout Differential LVPECL/LVDS to LVTTL Translator

文件：134.38 Kbytes Page：9 Pages

3.3V 1:2 Fanout Differential LVPECL/LVDS to LVTTL Translator

文件：165.16 Kbytes Page：8 Pages

封装/外壳：8-SOIC（0.154"，3.90mm 宽） 包装：卷带（TR） 描述：IC TRNSLTR UNIDIRECTIONAL 8SOIC 集成电路（IC） 转换器，电平移位器

1:2 Fanout Differential LVPECL to LVTTL Translator

Description The MC100EPT26 is a 1:2 Fanout Differential LVPECL/LVDS to LVTTL translator. Because LVPECL (Positive ECL) or LVDS levels are used only +3.3 V and ground are required. The small outline 8−lead package and the 1:2 fanout design of the EPT26 makes it ideal for applications which requi

3.3V 1:2 Fanout Differential LVPECL/LVDS to LVTTL Translator

文件：134.38 Kbytes Page：9 Pages