Clock Management Design Using Low Skew and Low Jitter Devices

Why Do We Need Clock Management? Can you imagine the chaos in our world if our clocks or watches were not synchronized to Greenwich Mean Time? How would trains, buses, and airplanes run on schedule? The miniseries Longitude was the story of a man who made a major technological breakthrough by inv

3.3V LVTTL/LVCMOS to Differential LVPECL Translator

3.3VLVTTL/LVCMOS to Differential LVPECL Translator The MC10EPT20 is a 3.3 V TTL/CMOS to differential PECL translator. Because PECL (Positive ECL) levels are used, only +3.3 V and ground are required. The small outline SOIC−8 package and the single gate of the EPT20 makes it ideal for those applic

3.3V LVTTL/LVCMOS to Differential LVPECL Translator

文件：140.95 Kbytes Page：10 Pages

3.3V LVTTL/LVCMOS to Differential LVPECL Translator

3.3VLVTTL/LVCMOS to Differential LVPECL Translator The MC10EPT20 is a 3.3 V TTL/CMOS to differential PECL translator. Because PECL (Positive ECL) levels are used, only +3.3 V and ground are required. The small outline SOIC−8 package and the single gate of the EPT20 makes it ideal for those applic

3.3V LVTTL/LVCMOS to Differential LVPECL Translator

文件：140.95 Kbytes Page：10 Pages

3.3V LVTTL/LVCMOS to Differential LVPECL Translator

文件：140.95 Kbytes Page：10 Pages

LVTTL/LVCMOS to Differential LVPECL Translator

文件：168.58 Kbytes Page：10 Pages

封装/外壳：8-TSSOP，8-MSOP（0.118"，3.00mm 宽） 包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：IC TRNSLTR UNIDIRECTIONAL 8TSSOP 集成电路（IC） 转换器，电平移位器

3.3V LVTTL/LVCMOS to Differential LVPECL Translator

文件：140.95 Kbytes Page：10 Pages

Evaluation Board Manual for High Frequency SOIC 8

文件：202.47 Kbytes Page：20 Pages