Clock Management Design Using Low Skew and Low Jitter Devices

Why Do We Need Clock Management? Can you imagine the chaos in our world if our clocks or watches were not synchronized to Greenwich Mean Time? How would trains, buses, and airplanes run on schedule? The miniseries Longitude was the story of a man who made a major technological breakthrough by inv

3.3V ECL Programmable Delay Chip

The MC10/100EP195 is a Programmable Delay Chip (PDC) designed primarily for clock deskewing and timing adjustment. It provides variable delay of a differential NECL/PECL input transition. The 100 Series contains temperature compensation. • Maximum Input Clock Frequency >1.2 GHz Typical • Progra

3.3V ECL Programmable Delay Chip

文件：220.27 Kbytes Page：20 Pages

3.3V ECL Programmable Delay Chip

文件：220.27 Kbytes Page：20 Pages

ECL Programmable Delay Chip

文件：156.09 Kbytes Page：19 Pages

封装/外壳：32-VFQFN 裸露焊盘 功能：可编程 包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：IC DELAY LINE 1024TAP PROG 32QFN 集成电路（IC） 延迟线

ECL Programmable Delay Chip

文件：156.09 Kbytes Page：19 Pages

封装/外壳：32-VFQFN 裸露焊盘 功能：可编程 包装：卷带（TR） 描述：IC DELAY LINE 1024TAP PROG 32QFN 集成电路（IC） 延迟线

3.3V ECL Programmable Delay Chip

文件：220.27 Kbytes Page：20 Pages

3.3V ECL Programmable Delay Chip

文件：189.11 Kbytes Page：17 Pages

3.3V ECL Programmable Delay Chip

文件：189.11 Kbytes Page：17 Pages