Single/Dual LVDS Line Receivers with ?쏧n-Path??Fail-Safe

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SINGLE / DUAL LVDS LINE RECEIVERS WITH IN - PATH FAIL - SAFE

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Low Skew Output Buffer

General Description The AV9172 is designed to generate low skew clocks for clock distribution in high-performance PCs and workstations. It uses phase-locked loop technology to align the phase and frequency of the output clocks with an input reference clock. Because the input to output skew is gua

ISO2-CMOS ST-BUS??FAMILY Digital Subscriber Interface Circuit Digital Network Interface Circuit

Description The MT9171 (DSIC) and MT9172 (DNIC) are multifunction devices capable of providing high speed, full duplex digital transmission up to 160 kbit/s over a twisted wire pair. They use adaptive echo cancelling techniques and transfer data in (2B+D) format compatible to the ISDN basic rat

ISO2-CMOS ST-BUS??FAMILY Digital Subscriber Interface Circuit Digital Network Interface Circuit

Description The MT9171 (DSIC) and MT9172 (DNIC) are multifunction devices capable of providing high speed, full duplex digital transmission up to 160 kbit/s over a twisted wire pair. They use adaptive echo cancelling techniques and transfer data in (2B+D) format compatible to the ISDN basic rat

ISO2-CMOS ST-BUS??FAMILY Digital Subscriber Interface Circuit Digital Network Interface Circuit

Description The MT9171 (DSIC) and MT9172 (DNIC) are multifunction devices capable of providing high speed, full duplex digital transmission up to 160 kbit/s over a twisted wire pair. They use adaptive echo cancelling techniques and transfer data in (2B+D) format compatible to the ISDN basic rat

HIGH SPEED PLL WITH BUILT-IN PRESCALER

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