ISO 15693, SHA3-256, 256-Bit User EEPROM Secure Authenticator

Benefits and Features ● Robust Countermeasures Protect against Security Attacks • All Stored Data Cryptographically Protected from Discovery ● Efficient Secure Hash Algorithm to Authenticate Peripherals • FIPS 202-Compliant SHA-3 Algorithm for Challenge/Response Authentication • FIPS 198-Com

ISO 15693, SHA3-256, 256-Bit User EEPROM Secure Authenticator

General Description The MAX66250 secure authenticator combines FIPS 202-compliant Secure Hash Algorithm (SHA-3) challengeand response authentication with secured EEPROM. The device provides a core set of cryptographic tools derived from integrated blocks including a SHA-3 engine, 256 bits of sec

ISO 15693、SHA3-256、256位用户EEPROM安全认证器

MAX66250安全认证器结合了符合FIPS 202标准的安全散列算法(SHA-3)质询和响应认证与安全EEPROM。\n\n 该器件提供了一套核心加密工具，这些加密工具由多种集成块衍生而来，包括一个SHA-3引擎、256位安全用户EEPROM、一个仅递减计数器，以及一个64位特有ROM识别号(ROM ID)。特有的ROM ID用作加密操作的基本输入参数，并在应用中用作电子序列号。该器件通过符合ISO/IEC 15693标准的RF接口进行通信。 • 可靠的防范措施助力防护安全攻击\n• 加密保护所有存储的数据，防止发生泄漏\n\n\n\n\n• 高效的安全散列算法对外设进行认证\n• 符合FIPS 202标准的SHA-3算法，用于质询/响应认证\n\n• 符合FIPS 198标准的键控散列消息认证代码(HMAC);

ISO 15693, SHA3-256, 256-Bit User EEPROM Secure Authenticator

Benefits and Features ● Robust Countermeasures Protect against Security Attacks • All Stored Data Cryptographically Protected from Discovery ● Efficient Secure Hash Algorithm to Authenticate Peripherals • FIPS 202-Compliant SHA-3 Algorithm for Challenge/Response Authentication • FIPS 198-Com

ISO 15693, SHA3-256, 256-Bit User EEPROM Secure Authenticator

Benefits and Features ● Robust Countermeasures Protect against Security Attacks • All Stored Data Cryptographically Protected from Discovery ● Efficient Secure Hash Algorithm to Authenticate Peripherals • FIPS 202-Compliant SHA-3 Algorithm for Challenge/Response Authentication • FIPS 198-Com

ISO 15693, SHA3-256, 256-Bit User EEPROM Secure Authenticator

Benefits and Features ● Robust Countermeasures Protect against Security Attacks • All Stored Data Cryptographically Protected from Discovery ● Efficient Secure Hash Algorithm to Authenticate Peripherals • FIPS 202-Compliant SHA-3 Algorithm for Challenge/Response Authentication • FIPS 198-Com

ISO 15693, SHA3-256, 256-Bit User EEPROM Secure Authenticator

General Description The MAX66250 secure authenticator combines FIPS 202-compliant Secure Hash Algorithm (SHA-3) challengeand response authentication with secured EEPROM. The device provides a core set of cryptographic tools derived from integrated blocks including a SHA-3 engine, 256 bits of sec

ISO 15693, SHA3-256, 256-Bit User EEPROM Secure Authenticator

General Description The MAX66250 secure authenticator combines FIPS 202-compliant Secure Hash Algorithm (SHA-3) challengeand response authentication with secured EEPROM. The device provides a core set of cryptographic tools derived from integrated blocks including a SHA-3 engine, 256 bits of sec

ISO 15693, SHA3-256, 256-Bit User EEPROM Secure Authenticator

Benefits and Features ● Robust Countermeasures Protect against Security Attacks • All Stored Data Cryptographically Protected from Discovery ● Efficient Secure Hash Algorithm to Authenticate Peripherals • FIPS 202-Compliant SHA-3 Algorithm for Challenge/Response Authentication • FIPS 198-Com

ISO 15693, SHA3-256, 256-Bit User EEPROM Secure Authenticator

Benefits and Features ● Robust Countermeasures Protect against Security Attacks • All Stored Data Cryptographically Protected from Discovery ● Efficient Secure Hash Algorithm to Authenticate Peripherals • FIPS 202-Compliant SHA-3 Algorithm for Challenge/Response Authentication • FIPS 198-Com

封装/外壳：8-SOIC（0.154"，3.90mm 宽） 包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：SECURE AUTH SHA3-256 EEPROM SOIC 集成电路（IC） 专用 IC

5120 X 8-BIT LINE MEMORY(FIFO/LIFO)

DESCRIPTION The M66250P/FP is a high-speed line memory with a FIFO (First In First Out) structure of 5120 - wordX8-bit configuration which uses high-performance silicon gate CMOS process technology.

5120 X 8-BIT LINE MEMORY(FIFO/LIFO)

DESCRIPTION The M66250P/FP is a high-speed line memory with a FIFO (First In First Out) structure of 5120 - wordX8-bit configuration which uses high-performance silicon gate CMOS process technology.

5120*8-BIT LINE MEMORY(FIFO/LIFO)

DESCRIPTION The M66250P/FP is a high-speed line memory with a FIFO (First In First Out) structure of 5120 - wordX8-bit configuration which uses high-performance silicon gate CMOS process technology.

5120 X 8-BIT LINE MEMORY(FIFO/LIFO)

DESCRIPTION The M66250P/FP is a high-speed line memory with a FIFO (First In First Out) structure of 5120 - wordX8-bit configuration which uses high-performance silicon gate CMOS process technology.

5120*8-BIT LINE MEMORY(FIFO/LIFO)

DESCRIPTION The M66250P/FP is a high-speed line memory with a FIFO (First In First Out) structure of 5120 - wordX8-bit configuration which uses high-performance silicon gate CMOS process technology.