ISO 15693, SHA3-256, 256-Bit User EEPROM Secure Authenticator

General Description The MAX66250 secure authenticator combines FIPS 202-compliant Secure Hash Algorithm (SHA-3) challengeand response authentication with secured EEPROM. The device provides a core set of cryptographic tools derived from integrated blocks including a SHA-3 engine, 256 bits of sec

ISO 15693, SHA3-256, 256-Bit User EEPROM Secure Authenticator

Benefits and Features ● Robust Countermeasures Protect against Security Attacks • All Stored Data Cryptographically Protected from Discovery ● Efficient Secure Hash Algorithm to Authenticate Peripherals • FIPS 202-Compliant SHA-3 Algorithm for Challenge/Response Authentication • FIPS 198-Com

5120 X 8-BIT LINE MEMORY(FIFO/LIFO)

DESCRIPTION The M66250P/FP is a high-speed line memory with a FIFO (First In First Out) structure of 5120 - wordX8-bit configuration which uses high-performance silicon gate CMOS process technology.

5120 X 8-BIT LINE MEMORY(FIFO/LIFO)

DESCRIPTION The M66250P/FP is a high-speed line memory with a FIFO (First In First Out) structure of 5120 - wordX8-bit configuration which uses high-performance silicon gate CMOS process technology.

5120*8-BIT LINE MEMORY(FIFO/LIFO)

DESCRIPTION The M66250P/FP is a high-speed line memory with a FIFO (First In First Out) structure of 5120 - wordX8-bit configuration which uses high-performance silicon gate CMOS process technology.

5120 X 8-BIT LINE MEMORY(FIFO/LIFO)

DESCRIPTION The M66250P/FP is a high-speed line memory with a FIFO (First In First Out) structure of 5120 - wordX8-bit configuration which uses high-performance silicon gate CMOS process technology.

5120*8-BIT LINE MEMORY(FIFO/LIFO)

DESCRIPTION The M66250P/FP is a high-speed line memory with a FIFO (First In First Out) structure of 5120 - wordX8-bit configuration which uses high-performance silicon gate CMOS process technology.