3 TO 8 LINE DECODER INVERTING

DESCRIPTION The M54/74HC138 is a high speed CMOS 3 TO 8 LINE DECODER fabricated in silicon gate C2MOS technology. It has the same high speed performance of LSTTL combinedwithtrue CMOSlowpower consumption. ■ HIGH SPEED tPD = 16 ns (TYP.) at VCC = 5 V ■ LOW POWER DISSIPATION ICC = 4 µA AT TA = 2

3 TO 8 LINE DECODER (INVERTING)

DESCRIPTION The M74HCT138 is an high speed CMOS 3 TO 8 LINE DECODER fabricated with silicon gate C2MOS technology. If the device is enabled, 3 binary select inputs (A, B, and C) determine which one of the outputs will go low. If enable input G1 is held low or either G2A or G2B is held high, the

3 TO 8 LINE DECODER (INVERTING)

3 TO 8 LINE DECODER INVERTING

DESCRIPTION The M54/74HC138 is a high speed CMOS 3 TO 8 LINE DECODER fabricated in silicon gate C2MOS technology. It has the same high speed performance of LSTTL combinedwithtrue CMOSlowpower consumption. ■ HIGH SPEED tPD = 16 ns (TYP.) at VCC = 5 V ■ LOW POWER DISSIPATION ICC = 4 µA AT TA = 2

3 TO 8 LINE DECODER (INVERTING)

DESCRIPTION The M74HCT138 is an high speed CMOS 3 TO 8 LINE DECODER fabricated with silicon gate C2MOS technology. If the device is enabled, 3 binary select inputs (A, B, and C) determine which one of the outputs will go low. If enable input G1 is held low or either G2A or G2B is held high, the

3 TO 8 LINE DECODER INVERTING

DESCRIPTION The M54/74HC138 is a high speed CMOS 3 TO 8 LINE DECODER fabricated in silicon gate C2MOS technology. It has the same high speed performance of LSTTL combinedwithtrue CMOSlowpower consumption. ■ HIGH SPEED tPD = 16 ns (TYP.) at VCC = 5 V ■ LOW POWER DISSIPATION ICC = 4 µA AT TA = 2

3 TO 8 LINE DECODER INVERTING

DESCRIPTION The M54/74HC138 is a high speed CMOS 3 TO 8 LINE DECODER fabricated in silicon gate C2MOS technology. It has the same high speed performance of LSTTL combinedwithtrue CMOSlowpower consumption. ■ HIGH SPEED tPD = 16 ns (TYP.) at VCC = 5 V ■ LOW POWER DISSIPATION ICC = 4 µA AT TA = 2

3 TO 8 LINE DECODER (INVERTING)

DESCRIPTION The M74HCT138 is an high speed CMOS 3 TO 8 LINE DECODER fabricated with silicon gate C2MOS technology. If the device is enabled, 3 binary select inputs (A, B, and C) determine which one of the outputs will go low. If enable input G1 is held low or either G2A or G2B is held high, the

3 TO 8 LINE DECODER (INVERTING)

DESCRIPTION The M74HCT138 is an high speed CMOS 3 TO 8 LINE DECODER fabricated with silicon gate C2MOS technology. If the device is enabled, 3 binary select inputs (A, B, and C) determine which one of the outputs will go low. If enable input G1 is held low or either G2A or G2B is held high, the

3 TO 8 LINE DECODER (INVERTING)

DESCRIPTION The M74HCT138 is an high speed CMOS 3 TO 8 LINE DECODER fabricated with silicon gate C2MOS technology. If the device is enabled, 3 binary select inputs (A, B, and C) determine which one of the outputs will go low. If enable input G1 is held low or either G2A or G2B is held high, the

封装/外壳：16-DIP（0.300"，7.62mm） 包装：托盘 描述：IC DECODER/DEMUX 1X3:8 16DIP 集成电路（IC） 信号开关，多路复用器，解码器

封装/外壳：16-SOIC（0.154"，3.90mm 宽） 包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：IC DECODER/DEMUX 1 X 3:8 16SO 集成电路（IC） 信号开关，多路复用器，解码器

3-to-8 line decoder/demultiplexer inverting

3-to-8 line decoder/demultiplexer; inverting

1. General description The 74HC138; 74HCT138 decodes three binary weighted address inputs (A0, A1 and A2) to eight mutually exclusive outputs (Y0 to Y7). The device features three enable inputs (E1, E2 and E3). Every output will be HIGH unless E1 and E2 are LOW and E3 is HIGH. This multiple ena

3-to-8 line decoder/demultiplexer; inverting

GENERAL DESCRIPTION The 74HC/HCT138 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Demultiplexing capability • Multiple input enable for easy expansion • Ideal for memory

3-to-8 line decoder/demultiplexer; inverting

3 TO 8 LINE DECODER DEMULTIPLEXER

文件：246.31 Kbytes Page：10 Pages