DUAL J-K FLIP FLOP WITH PRESET AND CLEAR

文件：323.47 Kbytes Page：11 Pages

DUAL J-K FLIP FLOP WITH PRESET AND CLEAR

DUAL J-K FLIP FLOP WITH PRESET AND CLEAR

DESCRIPTION The M74HC73 is an high speed CMOS DUAL J-K FLIP FLOP WITH CLEAR fabricated with silicon gate C2MOS technology ■ HIGH SPEED : fMAX = 80MHz (TYP.) at VCC = 6V ■ LOW POWER DISSIPATION: ICC =2µA(MAX.) at TA=25°C ■ HIGH NOISE IMMUNITY: VNIH = VNIL = 28 VCC (MIN.) ■ SYMMETRICAL OUTPUT

DUAL J-K FLIP FLOP WITH PRESET AND CLEAR

DESCRIPTION The M74HC73 is an high speed CMOS DUAL J-K FLIP FLOP WITH CLEAR fabricated with silicon gate C2MOS technology ■ HIGH SPEED : fMAX = 80MHz (TYP.) at VCC = 6V ■ LOW POWER DISSIPATION: ICC =2µA(MAX.) at TA=25°C ■ HIGH NOISE IMMUNITY: VNIH = VNIL = 28 VCC (MIN.) ■ SYMMETRICAL OUTPUT

DUAL J-K FLIP FLOP WITH PRESET AND CLEAR

DESCRIPTION The M74HC73 is an high speed CMOS DUAL J-K FLIP FLOP WITH CLEAR fabricated with silicon gate C2MOS technology ■ HIGH SPEED : fMAX = 80MHz (TYP.) at VCC = 6V ■ LOW POWER DISSIPATION: ICC =2µA(MAX.) at TA=25°C ■ HIGH NOISE IMMUNITY: VNIH = VNIL = 28 VCC (MIN.) ■ SYMMETRICAL OUTPUT

DUAL J-K FLIP FLOP WITH PRESET AND CLEAR

文件：323.47 Kbytes Page：11 Pages

DUAL J-K FLIP FLOP WITH PRESET AND CLEAR

文件：323.47 Kbytes Page：11 Pages

DUAL J-K FLIP FLOP WITH PRESET AND CLEAR

文件：323.47 Kbytes Page：11 Pages

DUAL J-K FLIP FLOP WITH PRESET AND CLEAR

文件：323.47 Kbytes Page：11 Pages

封装/外壳：14-SOIC（0.154"，3.90mm 宽） 功能：设置（预设）和复位 包装：卷带（TR） 描述：IC FF JK TYPE DUAL 1BIT 14SOP 集成电路（IC） 触发器

封装/外壳：14-TSSOP（0.173"，4.40mm 宽） 功能：设置（预设）和复位 包装：卷带（TR） 描述：IC FF JK TYPE DUAL 1BIT 14TSSOP 集成电路（IC） 触发器

DUAL J-K FLIP FLOP WITH PRESET AND CLEAR

文件：323.47 Kbytes Page：11 Pages

Dual JK flip-flop with reset; negative-edge trigger

Dual JK flip-flop with reset; negative-edge trigger

General description The 74HC73 is a high-speed Si-gate CMOS device and is pin compatible with low-power Schottky TTL (LSTTL). The 74HC73 is specified in compliance with JEDEC standard no. 7A. Features Low-power dissipation Complies with JEDEC standard no. 7A ESD protection:

Dual JK flip-flop with reset; negative-edge trigger

1. General description The 74HC73 is a dual negative edge triggered JK flip-flop with individual J, K, clock (nCP) and reset (nR) inputs and complementary nQ and nQ outputs. The J and K inputs must be stable one set-up time prior to the HIGH-to-LOW clock transition for predictable operation. (n

Dual JK flip-flop with reset; negative-edge trigger

General description The 74HC73 is a high-speed Si-gate CMOS device and is pin compatible with low-power Schottky TTL (LSTTL). The 74HC73 is specified in compliance with JEDEC standard no. 7A. Features Low-power dissipation Complies with JEDEC standard no. 7A ESD protection:

Dual JK flip-flop with reset; negative-edge trigger