OCTAL D TYPE FLIP FLOP

DESCRIPTION The M54/74HC377 is a high speed CMOS OCTALD-TYPE FLIP FLOP fabricated in silicon gate C2MOS technology. It has the same high speed performance of LSTTL combined with true CMOS low power consumption. Information at the D inputs meeting the setup time requirements is transferred to the

OCTAL D TYPE FLIP FLOP

DESCRIPTION The M74HC377 is an high speed CMOS OCTAL D TYPE FLIP FLOP fabricated with silicon gate C2MOS technology. Information at the D inputs meeting the setup time requirements is transferred to the Q outputs on the positive going edge of the clock pulse if the enable input Gis low. Clock t

Octal D-type flip-flop with data enable; positive-edge trigger

1. General description The 74HC377; 74HCT377 is an octal positive-edge triggered D-type flip-flop. The device features clock (CP) and data enable (E) inputs. When E is LOW, the outputs Qn assume the state of their corresponding Dn inputs that meet the set-up and hold time requirements on the LO

OCTAL D-TYPE FLIP-FLOP WITH DATA ENABLE POSITIVE EDGE TRIGGER

OCTAL D-TYPE FLIP-FLOP WITH DATA ENABLE POSITIVE EDGE TRIGGER

Octal D-type flip-flop with data enable; positive-edge trigger

GENERAL DESCRIPTION The 74HC/HCT377 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Ideal for addressable register applications • Data enable for address and data s

Octal D-type flip-flop with data enable; positive-edge trigger

GENERAL DESCRIPTION The 74HC/HCT377 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Ideal for addressable register applications • Data enable for address and data s

Octal D-type flip-flop with data enable; positive-edge trigger

1. General description The 74HC377; 74HCT377 is an octal positive-edge triggered D-type flip-flop. The device features clock (CP) and data enable (E) inputs. When E is LOW, the outputs Qn assume the state of their corresponding Dn inputs that meet the set-up and hold time requirements on the LO