HC353: DUAL 4 CHANNEL MULTIPLEXER 3 STATEOUTPUTINV. HC352: DUAL 4 CHANNEL MULTIPLEXERINV.

DESCRIPTION The M54/74HC352 and M54/74HC353 are high speed CMOS DUAL 4 CHANNEL MULTIPLEXERS INVERTING fabricated with silicon gate C2MOS technology. ■ HIGH SPEED tPD = 12 ns (TYP.) AT VCC = 5 V ■ LOW POWER DISSIPATION ICC = 4 µA (MAX.) AT TA = 25 °C ■ OUTPUT DRIVE CAPABILITY 10 LSTTL LOADS ■

HC353: DUAL 4 CHANNEL MULTIPLEXER 3 STATEOUTPUTINV. HC352: DUAL 4 CHANNEL MULTIPLEXERINV.

DESCRIPTION The M54/74HC352 and M54/74HC353 are high speed CMOS DUAL 4 CHANNEL MULTIPLEXERS INVERTING fabricated with silicon gate C2MOS technology. ■ HIGH SPEED tPD = 12 ns (TYP.) AT VCC = 5 V ■ LOW POWER DISSIPATION ICC = 4 µA (MAX.) AT TA = 25 °C ■ OUTPUT DRIVE CAPABILITY 10 LSTTL LOADS ■

HC353: DUAL 4 CHANNEL MULTIPLEXER 3 STATEOUTPUTINV. HC352: DUAL 4 CHANNEL MULTIPLEXERINV.

DESCRIPTION The M54/74HC352 and M54/74HC353 are high speed CMOS DUAL 4 CHANNEL MULTIPLEXERS INVERTING fabricated with silicon gate C2MOS technology. ■ HIGH SPEED tPD = 12 ns (TYP.) AT VCC = 5 V ■ LOW POWER DISSIPATION ICC = 4 µA (MAX.) AT TA = 25 °C ■ OUTPUT DRIVE CAPABILITY 10 LSTTL LOADS ■

HC353: DUAL 4 CHANNEL MULTIPLEXER 3 STATEOUTPUTINV. HC352: DUAL 4 CHANNEL MULTIPLEXERINV.

DESCRIPTION The M54/74HC352 and M54/74HC353 are high speed CMOS DUAL 4 CHANNEL MULTIPLEXERS INVERTING fabricated with silicon gate C2MOS technology. ■ HIGH SPEED tPD = 12 ns (TYP.) AT VCC = 5 V ■ LOW POWER DISSIPATION ICC = 4 µA (MAX.) AT TA = 25 °C ■ OUTPUT DRIVE CAPABILITY 10 LSTTL LOADS ■

HC353: DUAL 4 CHANNEL MULTIPLEXER 3 STATEOUTPUTINV. HC352: DUAL 4 CHANNEL MULTIPLEXERINV.

DESCRIPTION The M54/74HC352 and M54/74HC353 are high speed CMOS DUAL 4 CHANNEL MULTIPLEXERS INVERTING fabricated with silicon gate C2MOS technology. ■ HIGH SPEED tPD = 12 ns (TYP.) AT VCC = 5 V ■ LOW POWER DISSIPATION ICC = 4 µA (MAX.) AT TA = 25 °C ■ OUTPUT DRIVE CAPABILITY 10 LSTTL LOADS ■

Dual 4-to-1-line Data Selectors/Multiplexers (with 3-state outputs)

Description Each of these data selectors/multiplexers contains inverters and drivers to supply full binary decoding data selection to the AND-OR-invert gates. Separate strobe inputs (G) are provided for each of the two four-line sections. Features • High Speed Operation: tpd (Data to Y) = 13 ns

Dual 4-to-1-line Data Selectors/Multiplexers

Description Each of these data selectors/multiplexers contains inverters and drivers to supply full binary decoding data selection to the AND-OR-invert gates. Separate strobe inputs (G) are provided for each of the two four-line sections. Features • High Speed Operation: tpd (Data to Y) = 13 ns

Dual 4-to-1-line Data Selectors/Multiplexers

Description Each of these data selectors/multiplexers contains inverters and drivers to supply full binary decoding data selection to the AND-OR-invert gates. Separate strobe inputs (G) are provided for each of the two four-line sections. Features • High Speed Operation: tpd (Data to Y) = 13 ns

Dual 4-to-1-line Data Selectors/Multiplexers

Description Each of these data selectors/multiplexers contains inverters and drivers to supply full binary decoding data selection to the AND-OR-invert gates. Separate strobe inputs (G) are provided for each of the two four-line sections. Features • High Speed Operation: tpd (Data to Y) = 13 ns