9 BIT PARITY GENERATOR

DESCRIPTION The M54/74HC280 is a high speed CMOS 9-BIT PARITY GENERATOR fabricated in silicon gate C2MOS technology. It has the same high speed performance of LSTTL combined with true CMOS low consumption. ■ HIGH SPEED tPD = 22 ns (TYP.) at VCC = 5 V ■ LOW POWER DISSIPATION ICC =

9 BIT PARITY GENERATOR

DESCRIPTION The M54/74HC280 is a high speed CMOS 9-BIT PARITY GENERATOR fabricated in silicon gate C2MOS technology. It has the same high speed performance of LSTTL combined with true CMOS low consumption. ■ HIGH SPEED tPD = 22 ns (TYP.) at VCC = 5 V ■ LOW POWER DISSIPATION ICC =

9-bit parity generator

Features • High-speed: tPD = 22 ns (typ.) at VCC = 6 V • Low power dissipation: ICC = 4 μA (max.) at TA = 25 °C • High noise immunity: VNIH = VNIH = 28 % VCC (min) • Symmetrical output impedance: |IOH| = IOL = 4 mA (min.) • Balanced propagation delays: tPLH ≅ tPHL • Wide operating v

9位奇偶校验生成器

The M74HC280 is a high-speed CMOS 9-bit parity generator fabricated with silicon gate C2MOS technology.\n\n It is composed of nine data inputs (A to I) and odd/even parity outputs (ΣODD and ΣEVEN). The nine data inputs control the output conditions. When the number of high-level inputs is odd, ΣODD • High-speed: tPD = 22 ns (typ.) at VCC = 6 V \n• Low power dissipation: ICC = 4 μA (max.) at TA = 25 °C \n• High noise immunity: VNIH = VNIH = 28 % VCC (min) \n• Symmetrical output impedance: |IOH| = IOL = 4 mA (min.) \n• Balanced propagation delays: tPLH ≅ tPHL \n• Wide operating voltage range;

9-bit parity generator

Features • High-speed: tPD = 22 ns (typ.) at VCC = 6 V • Low power dissipation: ICC = 4 μA (max.) at TA = 25 °C • High noise immunity: VNIH = VNIH = 28 % VCC (min) • Symmetrical output impedance: |IOH| = IOL = 4 mA (min.) • Balanced propagation delays: tPLH ≅ tPHL • Wide operating v

9 BIT PARITY GENERATOR

DESCRIPTION The M54/74HC280 is a high speed CMOS 9-BIT PARITY GENERATOR fabricated in silicon gate C2MOS technology. It has the same high speed performance of LSTTL combined with true CMOS low consumption. ■ HIGH SPEED tPD = 22 ns (TYP.) at VCC = 5 V ■ LOW POWER DISSIPATION ICC =

9 BIT PARITY GENERATOR

DESCRIPTION The M54/74HC280 is a high speed CMOS 9-BIT PARITY GENERATOR fabricated in silicon gate C2MOS technology. It has the same high speed performance of LSTTL combined with true CMOS low consumption. ■ HIGH SPEED tPD = 22 ns (TYP.) at VCC = 5 V ■ LOW POWER DISSIPATION ICC =

9 BIT PARITY GENERATOR

DESCRIPTION The M54/74HC280 is a high speed CMOS 9-BIT PARITY GENERATOR fabricated in silicon gate C2MOS technology. It has the same high speed performance of LSTTL combined with true CMOS low consumption. ■ HIGH SPEED tPD = 22 ns (TYP.) at VCC = 5 V ■ LOW POWER DISSIPATION ICC =

9 BIT PARITY GENERATOR

DESCRIPTION The M54/74HC280 is a high speed CMOS 9-BIT PARITY GENERATOR fabricated in silicon gate C2MOS technology. It has the same high speed performance of LSTTL combined with true CMOS low consumption. ■ HIGH SPEED tPD = 22 ns (TYP.) at VCC = 5 V ■ LOW POWER DISSIPATION ICC =

9 BIT PARITY GENERATOR

DESCRIPTION The M54/74HC280 is a high speed CMOS 9-BIT PARITY GENERATOR fabricated in silicon gate C2MOS technology. It has the same high speed performance of LSTTL combined with true CMOS low consumption. ■ HIGH SPEED tPD = 22 ns (TYP.) at VCC = 5 V ■ LOW POWER DISSIPATION ICC =

9 BIT PARITY GENERATOR

DESCRIPTION The M54/74HC280 is a high speed CMOS 9-BIT PARITY GENERATOR fabricated in silicon gate C2MOS technology. It has the same high speed performance of LSTTL combined with true CMOS low consumption. ■ HIGH SPEED tPD = 22 ns (TYP.) at VCC = 5 V ■ LOW POWER DISSIPATION ICC =

丝印代码：74HC280；9-bit parity generator

Features • High-speed: tPD = 22 ns (typ.) at VCC = 6 V • Low power dissipation: ICC = 4 μA (max.) at TA = 25 °C • High noise immunity: VNIH = VNIH = 28 % VCC (min) • Symmetrical output impedance: |IOH| = IOL = 4 mA (min.) • Balanced propagation delays: tPLH ≅ tPHL • Wide operating v

丝印代码：HC280；9-bit parity generator

Features • High-speed: tPD = 22 ns (typ.) at VCC = 6 V • Low power dissipation: ICC = 4 μA (max.) at TA = 25 °C • High noise immunity: VNIH = VNIH = 28 % VCC (min) • Symmetrical output impedance: |IOH| = IOL = 4 mA (min.) • Balanced propagation delays: tPLH ≅ tPHL • Wide operating v

9 BIT PARITY GENERATOR

DESCRIPTION The M54/74HC280 is a high speed CMOS 9-BIT PARITY GENERATOR fabricated in silicon gate C2MOS technology. It has the same high speed performance of LSTTL combined with true CMOS low consumption. ■ HIGH SPEED tPD = 22 ns (TYP.) at VCC = 5 V ■ LOW POWER DISSIPATION ICC =

丝印代码：74HC280Y；9-bit parity generator

Features • High-speed: tPD = 22 ns (typ.) at VCC = 6 V • Low power dissipation: ICC = 4 μA (max.) at TA = 25 °C • High noise immunity: VNIH = VNIH = 28 % VCC (min) • Symmetrical output impedance: |IOH| = IOL = 4 mA (min.) • Balanced propagation delays: tPLH ≅ tPHL • Wide operating v

丝印代码：HC280Y；9-bit parity generator

Features • High-speed: tPD = 22 ns (typ.) at VCC = 6 V • Low power dissipation: ICC = 4 μA (max.) at TA = 25 °C • High noise immunity: VNIH = VNIH = 28 % VCC (min) • Symmetrical output impedance: |IOH| = IOL = 4 mA (min.) • Balanced propagation delays: tPLH ≅ tPHL • Wide operating v

封装/外壳：14-SOIC（0.154"，3.90mm 宽） 包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：IC PARITY GENERATOR 9-BIT 14SO 集成电路（IC） 奇偶校验发生器和校验器

封装/外壳：14-SOIC（0.154"，3.90mm 宽） 包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：IC PARITY GENERATOR 9-BIT 14SO 集成电路（IC） 奇偶校验发生器和校验器

9-bit odd/even parity generator/checker

GENERAL DESCRIPTION The 74HC/HCT280 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Word-length easily expanded by cascading • Similar pin configuration to the “180” for

9-bit odd/even parity generator/checker

GENERAL DESCRIPTION The 74HC/HCT280 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Word-length easily expanded by cascading • Similar pin configuration to the “180” for

9-bit Odd/Even Parity Generator/Checker

Description This parity generator/checker features odd/even outputs to facilitate operation of either odd or even parity applications. The word length capability is easily expanded by cascading devices. Features • High Speed Operation: tpd (Data to Even or Odd) = 22 ns typ (C L = 50 pF) • High

High Speed CMOS Logic 9-Bit Odd/Even Parity Generator/Checker

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