9-bit parity generator

Features • High-speed: tPD = 22 ns (typ.) at VCC = 6 V • Low power dissipation: ICC = 4 μA (max.) at TA = 25 °C • High noise immunity: VNIH = VNIH = 28 % VCC (min) • Symmetrical output impedance: |IOH| = IOL = 4 mA (min.) • Balanced propagation delays: tPLH ≅ tPHL • Wide operating v

9-bit odd/even parity generator/checker

GENERAL DESCRIPTION The 74HC/HCT280 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Word-length easily expanded by cascading • Similar pin configuration to the “180” for

9-bit odd/even parity generator/checker

1. General description The 74HC280; 74HCT280 is a 9-bit parity generator or checker. Both even and odd parity outputs are available. The even parity output (PE) is HIGH when an even number of data inputs (I0 to I8) is HIGH. The odd parity output (PO) is HIGH when an odd number of data inputs ar

9-bit odd/even parity generator/checker

1. General description The 74HC280; 74HCT280 is a 9-bit parity generator or checker. Both even and odd parity outputs are available. The even parity output (PE) is HIGH when an even number of data inputs (I0 to I8) is HIGH. The odd parity output (PO) is HIGH when an odd number of data inputs ar

9-bit odd/even parity generator/checker

GENERAL DESCRIPTION The 74HC/HCT280 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Word-length easily expanded by cascading • Similar pin configuration to the “180” for

9-bit odd/even parity generator/checker

GENERAL DESCRIPTION The 74HC/HCT280 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Word-length easily expanded by cascading • Similar pin configuration to the “180” for