3 TO 8 LINE DECODER INVERTING

DESCRIPTION The M54/74HC138 is a high speed CMOS 3 TO 8 LINE DECODER fabricated in silicon gate C2MOS technology. ■ HIGH SPEED tPD = 16 ns (TYP.) AT VCC = 5 V ■ LOW POWER DISSIPATION ICC = 4 µA AT TA = 25 °C ■ OUTPUT DRIVE CAPABILITY 10 LSTTL LOADS ■ BALANCED PROPAGATION D

3 TO 8 LINE DECODER (INVERTING)

DESCRIPTION The M54/74HC138 is a high speed CMOS 3 TO 8 LINE DECODER fabricated in silicon gate C2MOS technology. ■ HIGH SPEED tPD = 16 ns (TYP.) AT VCC = 5 V ■ LOW POWER DISSIPATION ICC = 4 µA AT TA = 25 °C ■ OUTPUT DRIVE CAPABILITY 10 LSTTL LOADS ■ BALANCED PROPAGATION D

3 TO 8 LINE DECODER (INVERTING)

3 TO 8 LINE DECODER INVERTING

DESCRIPTION The M54/74HC138 is a high speed CMOS 3 TO 8 LINE DECODER fabricated in silicon gate C2MOS technology. ■ HIGH SPEED tPD = 16 ns (TYP.) AT VCC = 5 V ■ LOW POWER DISSIPATION ICC = 4 µA AT TA = 25 °C ■ OUTPUT DRIVE CAPABILITY 10 LSTTL LOADS ■ BALANCED PROPAGATION D

3 TO 8 LINE DECODER (INVERTING)

DESCRIPTION The M54/74HC138 is a high speed CMOS 3 TO 8 LINE DECODER fabricated in silicon gate C2MOS technology. ■ HIGH SPEED tPD = 16 ns (TYP.) AT VCC = 5 V ■ LOW POWER DISSIPATION ICC = 4 µA AT TA = 25 °C ■ OUTPUT DRIVE CAPABILITY 10 LSTTL LOADS ■ BALANCED PROPAGATION D

3 TO 8 LINE DECODER INVERTING

DESCRIPTION The M54/74HC138 is a high speed CMOS 3 TO 8 LINE DECODER fabricated in silicon gate C2MOS technology. ■ HIGH SPEED tPD = 16 ns (TYP.) AT VCC = 5 V ■ LOW POWER DISSIPATION ICC = 4 µA AT TA = 25 °C ■ OUTPUT DRIVE CAPABILITY 10 LSTTL LOADS ■ BALANCED PROPAGATION D

3 TO 8 LINE DECODER (INVERTING)

DESCRIPTION The M54/74HC138 is a high speed CMOS 3 TO 8 LINE DECODER fabricated in silicon gate C2MOS technology. ■ HIGH SPEED tPD = 16 ns (TYP.) AT VCC = 5 V ■ LOW POWER DISSIPATION ICC = 4 µA AT TA = 25 °C ■ OUTPUT DRIVE CAPABILITY 10 LSTTL LOADS ■ BALANCED PROPAGATION D

3 TO 8 LINE DECODER INVERTING

DESCRIPTION The M54/74HC138 is a high speed CMOS 3 TO 8 LINE DECODER fabricated in silicon gate C2MOS technology. ■ HIGH SPEED tPD = 16 ns (TYP.) AT VCC = 5 V ■ LOW POWER DISSIPATION ICC = 4 µA AT TA = 25 °C ■ OUTPUT DRIVE CAPABILITY 10 LSTTL LOADS ■ BALANCED PROPAGATION D

3 TO 8 LINE DECODER (INVERTING)

DESCRIPTION The M54/74HC138 is a high speed CMOS 3 TO 8 LINE DECODER fabricated in silicon gate C2MOS technology. ■ HIGH SPEED tPD = 16 ns (TYP.) AT VCC = 5 V ■ LOW POWER DISSIPATION ICC = 4 µA AT TA = 25 °C ■ OUTPUT DRIVE CAPABILITY 10 LSTTL LOADS ■ BALANCED PROPAGATION D

3 TO 8 LINE DECODER (INVERTING)

DESCRIPTION The M54/74HC138 is a high speed CMOS 3 TO 8 LINE DECODER fabricated in silicon gate C2MOS technology. ■ HIGH SPEED tPD = 16 ns (TYP.) AT VCC = 5 V ■ LOW POWER DISSIPATION ICC = 4 µA AT TA = 25 °C ■ OUTPUT DRIVE CAPABILITY 10 LSTTL LOADS ■ BALANCED PROPAGATION D

封装/外壳：16-SOIC（0.154"，3.90mm 宽） 包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：IC DECODER/DEMUX 1 X 3:8 16SO 集成电路（IC） 信号开关，多路复用器，解码器

封装/外壳：16-TSSOP（0.173"，4.40mm 宽） 包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：IC DECODER/DEMUX 1X3:8 16TSSOP 集成电路（IC） 信号开关，多路复用器，解码器

3-to-8 line decoder/demultiplexer; inverting

GENERAL DESCRIPTION The 74HC/HCT138 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Demultiplexing capability • Multiple input enable for easy expansion • Ideal for memory

3 TO 8 LINE DECODER DEMULTIPLEXER

Description The 74HC138 is a high speed CMOS device. The device accepts a three bit binary weighted address on input pins A0, A1 and A2 and when enabled will produce one active low output with the remaing seven being high. There are two active LOW enable inputs E1 and E2, and one active HIGH en

3-to-8 line decoder/demultiplexer inverting

1?뭥f?? Decoder/ Demultiplexer High?뭁erformance Silicon?묰ate CMOS

文件：140.61 Kbytes Page：9 Pages

3-to-8 Line Decoder/Demultiplexer; Inverting

文件：229.08 Kbytes Page：5 Pages