QUAD 2-INPUT SCHMITT NAND GATE

DESCRIPTION The M54/74HC132 is a high speed CMOSQUAD2-INPUT SCHMITT NAND GATE fabricated in silicon gate C2MOS technology. It has the same high speed performance of LSTTL combined with true CMOS low power consumption. Pin configuration and function are identical to those of the M54/74HC00.

QUAD 2-INPUT SCHMITT NAND GATE

DESCRIPTION The M54/74HC132 is a high speed CMOSQUAD2-INPUT SCHMITT NAND GATE fabricated in silicon gate C2MOS technology. It has the same high speed performance of LSTTL combined with true CMOS low power consumption. Pin configuration and function are identical to those of the M54/74HC00.

Quad 2?묲nput NAND Gate with Schmitt?뭈rigger Inputs High?뭁erformance Silicon?묰ate CMOS

Quad 2−Input NAND Gate with Schmitt−Trigger Inputs High−Performance Silicon−Gate CMOS The 74HC132 is identical in pinout to the LS132. The device inputs are compatible with standard CMOS outputs; with pull−up resistors, they are compatible with LSTTL outputs. The HC132 can be used to enhance no

Quad 2-input NAND Schmitt trigger

1. General description The 74HC132; 74HCT132 is a quad 2-input NAND gate with Schmitt-trigger inputs. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. Schmitt trigger inputs transform slowly changing input signals

High Speed CMOS Logic

Features High Speed: tPD = 11ns @ 5V (Typ.) Low Input Current: 1μA Output Drive Capability: 10 LSTTL loads Outputs directly interface CMOS, NMOS and TTL Operating Voltage Range: 2V to 6V CMOS High Noise Immunity Function compatible with 74LS132.

Quad 2-input NAND Schmitt trigger

GENERAL DESCRIPTION The 74HC/HCT132 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT132 contain four 2-input NAND gates which accept standard input signals. They are capable

High Speed CMOS Logic

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