RAD HARD DUAL J-K FLIP FLOP WITH PRESET AND CLEAR

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Rad-hard high speed 2 to 6 V CMOS logic series

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RAD HARD DUAL J-K FLIP FLOP WITH PRESET AND CLEAR

文件：317.55 Kbytes Page：11 Pages

CDx4HC73 CD74HCT73 Dual J-K Flip-Flop with Reset Negative-Edge Trigger

1 Features • Hysteresis on clock inputs for improved noise immunity and increased input rise and fall times • Asynchronous reset • Complementary outputs • Buffered inputs • Typical fMAX = 60 MHz at VCC = 5 V, CL = 15 pF, TA = 25℃ • Fanout (over temperature range) – Standard outputs: 10 LS

Dual J-K Flip-Flop with Reset Negative-Edge Trigger

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Dual J-K Flip-Flop with Reset Negative-Edge Trigger

文件：1.00769 Mbytes Page：18 Pages

Dual J-K Flip-Flop with Reset Negative-Edge Trigger

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Dual J-K Flip-Flop with Reset Negative-Edge Trigger

文件：422.72 Kbytes Page：15 Pages