CDx4HC73 CD74HCT73 Dual J-K Flip-Flop with Reset Negative-Edge Trigger

1 Features • Hysteresis on clock inputs for improved noise immunity and increased input rise and fall times • Asynchronous reset • Complementary outputs • Buffered inputs • Typical fMAX = 60 MHz at VCC = 5 V, CL = 15 pF, TA = 25℃ • Fanout (over temperature range) – Standard outputs: 10 LS

具有复位功能的高速 CMOS 逻辑双路负边沿触发式 J-K 触发器

• 时钟输入迟滞，改进了抗扰度并增加了输入上升和下降时间\n• 互补输出\n• 当 VCC = 5V， CL = 15pF，TA = 25℃ 时 fMAX 典型值 = 60MHz\n• 标准输出：10 个 LSTTL 负载\n• 宽工作温度范围：–55℃ 至 125℃\n• 与 LSTTL 逻辑 IC 相比，功耗显著降低\n• 工作电压为 2 V 至 6V\n• HCT 类型 \n• 直接 LSTTL 输入逻辑兼容性， VIL = 0.8V（最大值），VIH = 2V（最小值）\n• CMOS 输入兼容性，当电压为 VOL、VOH时，II ≤ 1µA;

Dual J-K Flip-Flop with Reset Negative-Edge Trigger

文件：266.53 Kbytes Page：13 Pages

Dual J-K Flip-Flop with Reset Negative-Edge Trigger

文件：422.72 Kbytes Page：15 Pages

Dual J-K Flip-Flop with Reset Negative-Edge Trigger

文件：452.31 Kbytes Page：15 Pages

Dual J-K Flip-Flop with Reset Negative-Edge Trigger

文件：1.00769 Mbytes Page：18 Pages

丝印代码：CD54HC73F；CDx4HC73 CD74HCT73 Dual J-K Flip-Flop with Reset Negative-Edge Trigger

1 Features • Hysteresis on clock inputs for improved noise immunity and increased input rise and fall times • Asynchronous reset • Complementary outputs • Buffered inputs • Typical fMAX = 60 MHz at VCC = 5 V, CL = 15 pF, TA = 25℃ • Fanout (over temperature range) – Standard outputs: 10 LS

丝印代码：CD54HC73F；CDx4HC73 CD74HCT73 Dual J-K Flip-Flop with Reset Negative-Edge Trigger

1 Features • Hysteresis on clock inputs for improved noise immunity and increased input rise and fall times • Asynchronous reset • Complementary outputs • Buffered inputs • Typical fMAX = 60 MHz at VCC = 5 V, CL = 15 pF, TA = 25℃ • Fanout (over temperature range) – Standard outputs: 10 LS

丝印代码：CD54HC73F；Dual J-K Flip-Flop with Reset Negative-Edge Trigger

文件：1.00769 Mbytes Page：18 Pages

丝印代码：5962-8515301CA；CDx4HC73 CD74HCT73 Dual J-K Flip-Flop with Reset Negative-Edge Trigger

1 Features • Hysteresis on clock inputs for improved noise immunity and increased input rise and fall times • Asynchronous reset • Complementary outputs • Buffered inputs • Typical fMAX = 60 MHz at VCC = 5 V, CL = 15 pF, TA = 25℃ • Fanout (over temperature range) – Standard outputs: 10 LS

丝印代码：5962-8515301CA；CDx4HC73 CD74HCT73 Dual J-K Flip-Flop with Reset Negative-Edge Trigger

1 Features • Hysteresis on clock inputs for improved noise immunity and increased input rise and fall times • Asynchronous reset • Complementary outputs • Buffered inputs • Typical fMAX = 60 MHz at VCC = 5 V, CL = 15 pF, TA = 25℃ • Fanout (over temperature range) – Standard outputs: 10 LS

Dual J-K Flip-Flop with Reset Negative-Edge Trigger

文件：422.72 Kbytes Page：15 Pages

Dual J-K Flip-Flop with Reset Negative-Edge Trigger

文件：452.31 Kbytes Page：15 Pages

Dual J-K Flip-Flop with Reset Negative-Edge Trigger

文件：1.00769 Mbytes Page：18 Pages

Dual J-K Flip-Flop with Reset Negative-Edge Trigger

文件：422.72 Kbytes Page：15 Pages

Dual J-K Flip-Flop with Reset Negative-Edge Trigger

文件：266.53 Kbytes Page：13 Pages

Dual J-K Flip-Flop with Reset Negative-Edge Trigger

文件：422.72 Kbytes Page：15 Pages

Dual J-K Flip-Flop with Reset Negative-Edge Trigger

文件：266.53 Kbytes Page：13 Pages

Dual J-K Flip-Flop with Reset Negative-Edge Trigger

文件：452.31 Kbytes Page：15 Pages

丝印代码：5962-8515301CA；Dual J-K Flip-Flop with Reset Negative-Edge Trigger

文件：1.00769 Mbytes Page：18 Pages

DUAL J-K FLIP FLOP WITH PRESET AND CLEAR

DESCRIPTION The M74HC73 is an high speed CMOS DUAL J-K FLIP FLOP WITH CLEAR fabricated with silicon gate C2MOS technology ■ HIGH SPEED : fMAX = 80MHz (TYP.) at VCC = 6V ■ LOW POWER DISSIPATION: ICC =2µA(MAX.) at TA=25°C ■ HIGH NOISE IMMUNITY: VNIH = VNIL = 28 VCC (MIN.) ■ SYMMETRICAL OUTPUT

Dual J-K Flip-Flops with Clear

文件：140.08 Kbytes Page：6 Pages

Dual J-K Flip-Flops with Clear

文件：140.08 Kbytes Page：6 Pages