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ISPLSI2064VL-100LJ44中文资料
ISPLSI2064VL-100LJ44数据手册规格书PDF详情
Description
The ispLSI 2064VL is a High Density Programmable Logic Device available in 64 and 32 I/O-pin versions. The device contains 64 Registers, four Dedicated Input pins, three Dedicated Clock Input pins, two dedicated Global OE input pins and a Global Routing Pool (GRP).
Features
• SuperFAST HIGH DENSITY PROGRAMMABLE LOGIC
— 2000 PLD Gates
— 64 and 32 I/O Pin Versions, Four Dedicated Inputs
— 64 Registers
— High Speed Global Interconnect
— Wide Input Gating for Fast Counters, State
Machines, Address Decoders, etc.
— Small Logic Block Size for Random Logic
— 100 Functional, JEDEC and Pinout Compatible with
ispLSI 2064V and 2064VE Devices
• 2.5V LOW VOLTAGE 2064 ARCHITECTURE
— Interfaces with Standard 3.3V TTL Devices (Inputs
and I/Os are 3.3V Tolerant)
— 60 mA Typical Active Current
• HIGH-PERFORMANCE E2CMOS® TECHNOLOGY
— fmax = 165MHz Maximum Operating Frequency
— tpd = 5.5ns Propagation Delay
— Electrically Erasable and Reprogrammable
— Non-Volatile
— 100 Tested at Time of Manufacture
— Unused Product Term Shutdown Saves Power
• IN-SYSTEM PROGRAMMABLE
— 2.5V In-System Programmability (ISP™) Using
Boundary Scan Test Access Port (TAP)
— Open-Drain Output Option for Flexible Bus Interface
Capability, Allowing Easy Implementation of Wired-OR
or Bus Arbitration Logic
— Increased Manufacturing Yields, Reduced Time-toMarket
and Improved Product Quality
— Reprogram Soldered Devices for Faster Prototyping
• 100 IEEE 1149.1 BOUNDARY SCAN TESTABLE
• THE EASE OF USE AND FAST SYSTEM SPEED OF
PLDs WITH THE DENSITY AND FLEXIBILITY OF FPGAs
— Enhanced Pin Locking Capability
— Three Dedicated Clock Input Pins
— Synchronous and Asynchronous Clocks
— Programmable Output Slew Rate Control
— Flexible Pin Placement
— Optimized Global Routing Pool Provides Global
Interconnectivity
• ispDesignEXPERT™ – LOGIC COMPILER AND COMPLETE
ISP DEVICE DESIGN SYSTEMS FROM HDL
SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING
— Superior Quality of Results
— Tightly Integrated with Leading CAE Vendor Tools
— Productivity Enhancing Timing Analyzer, Explore
Tools, Timing Simulator and ispANALYZER™
— PC and UNIX Platforms
ISPLSI2064VL-100LJ44产品属性
- 类型
描述
- 型号
ISPLSI2064VL-100LJ44
- 功能描述
CPLD - 复杂可编程逻辑器件 USE ispMACH 4000B
- RoHS
否
- 制造商
Lattice
- 存储类型
EEPROM
- 大电池数量
128
- 最大工作频率
333 MHz
- 延迟时间
2.7 ns
- 可编程输入/输出端数量
64
- 工作电源电压
3.3 V
- 最大工作温度
+ 90 C
- 最小工作温度
0 C
- 封装/箱体
TQFP-100
供应商 | 型号 | 品牌 | 批号 | 封装 | 库存 | 备注 | 价格 |
---|---|---|---|---|---|---|---|
LATTICE |
23+ |
NA |
25060 |
只做进口原装,终端工厂免费送样 |
|||
LATTICE |
24+ |
FPGA |
5068 |
原装现货 |
|||
LATTICE |
24+ |
NA |
2000 |
只做原装正品现货 欢迎来电查询15919825718 |
|||
LATTICE |
23+ |
QFP |
50000 |
全新原装正品现货,支持订货 |
|||
LATTICE |
21+ |
QFP |
10000 |
原装现货假一罚十 |
|||
LATTICE |
0620+ |
QFP |
260 |
一级代理,专注军工、汽车、医疗、工业、新能源、电力 |
|||
LATTICE |
23+ |
QFP |
7000 |
||||
LATTICE |
20+ |
QFP |
260 |
进口原装现货,假一赔十 |
|||
LATTICE |
24+ |
QFP |
21580 |
原装现货 |
|||
LATTICE/莱迪斯 |
23+ |
QFP |
50000 |
全新原装正品现货,支持订货 |
ISPLSI2064VL-100LJ44 资料下载更多...
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Datasheet数据表PDF页码索引
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