LVDS Description and Family Characteristics

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丝印代码：LVDS047；LVDS QUAD DIFFERENTIAL LINE DRIVER

FEATURES · >400 Mbps (200 MHz) Signaling Rates · Flow-Through Pinout Simplifies PCB Layout · 300 ps Maximum Differential Skew · Propagation Delay Times 1.8 ns (Typical) · 3.3 V Power Supply Design · ±350 mV Differential Signaling · High Impedance on LVDS Outputs on Power Down · Conforms t

丝印代码：LVDS047；LVDS QUAD DIFFERENTIAL LINE DRIVER

FEATURES · >400 Mbps (200 MHz) Signaling Rates · Flow-Through Pinout Simplifies PCB Layout · 300 ps Maximum Differential Skew · Propagation Delay Times 1.8 ns (Typical) · 3.3 V Power Supply Design · ±350 mV Differential Signaling · High Impedance on LVDS Outputs on Power Down · Conforms t

丝印代码：LVDS047；LVDS QUAD DIFFERENTIAL LINE DRIVER

FEATURES · >400 Mbps (200 MHz) Signaling Rates · Flow-Through Pinout Simplifies PCB Layout · 300 ps Maximum Differential Skew · Propagation Delay Times 1.8 ns (Typical) · 3.3 V Power Supply Design · ±350 mV Differential Signaling · High Impedance on LVDS Outputs on Power Down · Conforms t

丝印代码：LVDS047；LVDS QUAD DIFFERENTIAL LINE DRIVER

FEATURES · >400 Mbps (200 MHz) Signaling Rates · Flow-Through Pinout Simplifies PCB Layout · 300 ps Maximum Differential Skew · Propagation Delay Times 1.8 ns (Typical) · 3.3 V Power Supply Design · ±350 mV Differential Signaling · High Impedance on LVDS Outputs on Power Down · Conforms t

丝印代码：LVDS047；LVDS QUAD DIFFERENTIAL LINE DRIVER

FEATURES · >400 Mbps (200 MHz) Signaling Rates · Flow-Through Pinout Simplifies PCB Layout · 300 ps Maximum Differential Skew · Propagation Delay Times 1.8 ns (Typical) · 3.3 V Power Supply Design · ±350 mV Differential Signaling · High Impedance on LVDS Outputs on Power Down · Conforms t

丝印代码：LVDS047；LVDS QUAD DIFFERENTIAL LINE DRIVER

FEATURES · >400 Mbps (200 MHz) Signaling Rates · Flow-Through Pinout Simplifies PCB Layout · 300 ps Maximum Differential Skew · Propagation Delay Times 1.8 ns (Typical) · 3.3 V Power Supply Design · ±350 mV Differential Signaling · High Impedance on LVDS Outputs on Power Down · Conforms t

丝印代码：LVDS047；LVDS QUAD DIFFERENTIAL LINE DRIVER

FEATURES · >400 Mbps (200 MHz) Signaling Rates · Flow-Through Pinout Simplifies PCB Layout · 300 ps Maximum Differential Skew · Propagation Delay Times 1.8 ns (Typical) · 3.3 V Power Supply Design · ±350 mV Differential Signaling · High Impedance on LVDS Outputs on Power Down · Conforms t

丝印代码：LVDS047；LVDS QUAD DIFFERENTIAL LINE DRIVER

FEATURES · >400 Mbps (200 MHz) Signaling Rates · Flow-Through Pinout Simplifies PCB Layout · 300 ps Maximum Differential Skew · Propagation Delay Times 1.8 ns (Typical) · 3.3 V Power Supply Design · ±350 mV Differential Signaling · High Impedance on LVDS Outputs on Power Down · Conforms t

丝印代码：LVDS047；LVDS QUAD DIFFERENTIAL LINE DRIVER

FEATURES · >400 Mbps (200 MHz) Signaling Rates · Flow-Through Pinout Simplifies PCB Layout · 300 ps Maximum Differential Skew · Propagation Delay Times 1.8 ns (Typical) · 3.3 V Power Supply Design · ±350 mV Differential Signaling · High Impedance on LVDS Outputs on Power Down · Conforms t

丝印代码：LVDS047；LVDS QUAD DIFFERENTIAL LINE DRIVER

FEATURES · >400 Mbps (200 MHz) Signaling Rates · Flow-Through Pinout Simplifies PCB Layout · 300 ps Maximum Differential Skew · Propagation Delay Times 1.8 ns (Typical) · 3.3 V Power Supply Design · ±350 mV Differential Signaling · High Impedance on LVDS Outputs on Power Down · Conforms t

丝印代码：LVDS047；LVDS QUAD DIFFERENTIAL LINE DRIVER

FEATURES · >400 Mbps (200 MHz) Signaling Rates · Flow-Through Pinout Simplifies PCB Layout · 300 ps Maximum Differential Skew · Propagation Delay Times 1.8 ns (Typical) · 3.3 V Power Supply Design · ±350 mV Differential Signaling · High Impedance on LVDS Outputs on Power Down · Conforms t

丝印代码：LVDS048A；LVDS QUAD DIFFERENTIAL LINE RECEIVER

FEATURES · >400 Mbps (200 MHz) Signaling Rates · Flow-Through Pinout Simplifies PCB Layout · 50 ps Channel-to-Channel Skew (Typ) · 200 ps Differential Skew (Typ) · Propagation Delay Times 2.7 ns (Typ) · 3.3-V Power Supply Design · High Impedance LVDS Inputs on Power Down · Low-Power Dissip

丝印代码：LVDS048A；LVDS QUAD DIFFERENTIAL LINE RECEIVER

FEATURES · >400 Mbps (200 MHz) Signaling Rates · Flow-Through Pinout Simplifies PCB Layout · 50 ps Channel-to-Channel Skew (Typ) · 200 ps Differential Skew (Typ) · Propagation Delay Times 2.7 ns (Typ) · 3.3-V Power Supply Design · High Impedance LVDS Inputs on Power Down · Low-Power Dissip

丝印代码：LVDS048A；LVDS QUAD DIFFERENTIAL LINE RECEIVER

FEATURES · >400 Mbps (200 MHz) Signaling Rates · Flow-Through Pinout Simplifies PCB Layout · 50 ps Channel-to-Channel Skew (Typ) · 200 ps Differential Skew (Typ) · Propagation Delay Times 2.7 ns (Typ) · 3.3-V Power Supply Design · High Impedance LVDS Inputs on Power Down · Low-Power Dissip

丝印代码：LVDS048A；LVDS QUAD DIFFERENTIAL LINE RECEIVER

FEATURES · >400 Mbps (200 MHz) Signaling Rates · Flow-Through Pinout Simplifies PCB Layout · 50 ps Channel-to-Channel Skew (Typ) · 200 ps Differential Skew (Typ) · Propagation Delay Times 2.7 ns (Typ) · 3.3-V Power Supply Design · High Impedance LVDS Inputs on Power Down · Low-Power Dissip

丝印代码：LVDS048A；LVDS QUAD DIFFERENTIAL LINE RECEIVER

FEATURES · >400 Mbps (200 MHz) Signaling Rates · Flow-Through Pinout Simplifies PCB Layout · 50 ps Channel-to-Channel Skew (Typ) · 200 ps Differential Skew (Typ) · Propagation Delay Times 2.7 ns (Typ) · 3.3-V Power Supply Design · High Impedance LVDS Inputs on Power Down · Low-Power Dissip

丝印代码：LVDS049；SN65LVDS049 Dual-LVDS Differential Drivers and Receivers

1 Features 1• DS90LV049 Compatible • Up to 400-Mbps Signaling Rates • Flow-Through Pinout • 50-ps Driver Channel-to-Channel Skew (Typical) • 50-ps Receiver Channel-to-Channel Skew (Typical) • 3.3-V Power Supply • High-Impedance Disable for All Outputs • Internal Fail-safe Biasing of Recei

丝印代码：LVDS049；SN65LVDS049 Dual-LVDS Differential Drivers and Receivers

1 Features 1• DS90LV049 Compatible • Up to 400-Mbps Signaling Rates • Flow-Through Pinout • 50-ps Driver Channel-to-Channel Skew (Typical) • 50-ps Receiver Channel-to-Channel Skew (Typical) • 3.3-V Power Supply • High-Impedance Disable for All Outputs • Internal Fail-safe Biasing of Recei

丝印代码：LVDS049；SN65LVDS049 Dual-LVDS Differential Drivers and Receivers

1 Features 1• DS90LV049 Compatible • Up to 400-Mbps Signaling Rates • Flow-Through Pinout • 50-ps Driver Channel-to-Channel Skew (Typical) • 50-ps Receiver Channel-to-Channel Skew (Typical) • 3.3-V Power Supply • High-Impedance Disable for All Outputs • Internal Fail-safe Biasing of Recei

丝印代码：LVDS049；SN65LVDS049 Dual-LVDS Differential Drivers and Receivers

1 Features 1• DS90LV049 Compatible • Up to 400-Mbps Signaling Rates • Flow-Through Pinout • 50-ps Driver Channel-to-Channel Skew (Typical) • 50-ps Receiver Channel-to-Channel Skew (Typical) • 3.3-V Power Supply • High-Impedance Disable for All Outputs • Internal Fail-safe Biasing of Recei

丝印代码：LVDS049；SN65LVDS049 Dual-LVDS Differential Drivers and Receivers

1 Features 1• DS90LV049 Compatible • Up to 400-Mbps Signaling Rates • Flow-Through Pinout • 50-ps Driver Channel-to-Channel Skew (Typical) • 50-ps Receiver Channel-to-Channel Skew (Typical) • 3.3-V Power Supply • High-Impedance Disable for All Outputs • Internal Fail-safe Biasing of Recei

丝印代码：LVDS049；SN65LVDS049 Dual-LVDS Differential Drivers and Receivers

1 Features 1• DS90LV049 Compatible • Up to 400-Mbps Signaling Rates • Flow-Through Pinout • 50-ps Driver Channel-to-Channel Skew (Typical) • 50-ps Receiver Channel-to-Channel Skew (Typical) • 3.3-V Power Supply • High-Impedance Disable for All Outputs • Internal Fail-safe Biasing of Recei

丝印代码：LVDS104；SN65LVDS10x 4-Port LVDS and 4-Port TTL-to-LVDS Repeaters

1 Features 1• Receiver and Drivers Meet or Exceed the Requirements of ANSI EIA/TIA-644 Standard – SN65LVDS105 Receives Low-Voltage TTL (LVTTL) Levels – SN65LVDS104 Receives Differential Input Levels, ±100 mV • Typical Data Signaling Rates to 400 Mbps or Clock Frequencies to 400 MHz • Oper

丝印代码：LVDS104；SN65LVDS10x 4-Port LVDS and 4-Port TTL-to-LVDS Repeaters

1 Features 1• Receiver and Drivers Meet or Exceed the Requirements of ANSI EIA/TIA-644 Standard – SN65LVDS105 Receives Low-Voltage TTL (LVTTL) Levels – SN65LVDS104 Receives Differential Input Levels, ±100 mV • Typical Data Signaling Rates to 400 Mbps or Clock Frequencies to 400 MHz • Oper

丝印代码：LVDS104；SN65LVDS10x 4-Port LVDS and 4-Port TTL-to-LVDS Repeaters

1 Features 1• Receiver and Drivers Meet or Exceed the Requirements of ANSI EIA/TIA-644 Standard – SN65LVDS105 Receives Low-Voltage TTL (LVTTL) Levels – SN65LVDS104 Receives Differential Input Levels, ±100 mV • Typical Data Signaling Rates to 400 Mbps or Clock Frequencies to 400 MHz • Oper

丝印代码：LVDS104；SN65LVDS10x 4-Port LVDS and 4-Port TTL-to-LVDS Repeaters

1 Features 1• Receiver and Drivers Meet or Exceed the Requirements of ANSI EIA/TIA-644 Standard – SN65LVDS105 Receives Low-Voltage TTL (LVTTL) Levels – SN65LVDS104 Receives Differential Input Levels, ±100 mV • Typical Data Signaling Rates to 400 Mbps or Clock Frequencies to 400 MHz • Oper

丝印代码：LVDS104；SN65LVDS10x 4-Port LVDS and 4-Port TTL-to-LVDS Repeaters

1 Features 1• Receiver and Drivers Meet or Exceed the Requirements of ANSI EIA/TIA-644 Standard – SN65LVDS105 Receives Low-Voltage TTL (LVTTL) Levels – SN65LVDS104 Receives Differential Input Levels, ±100 mV • Typical Data Signaling Rates to 400 Mbps or Clock Frequencies to 400 MHz • Oper

丝印代码：LVDS104；SN65LVDS10x 4-Port LVDS and 4-Port TTL-to-LVDS Repeaters

1 Features 1• Receiver and Drivers Meet or Exceed the Requirements of ANSI EIA/TIA-644 Standard – SN65LVDS105 Receives Low-Voltage TTL (LVTTL) Levels – SN65LVDS104 Receives Differential Input Levels, ±100 mV • Typical Data Signaling Rates to 400 Mbps or Clock Frequencies to 400 MHz • Oper

丝印代码：LVDS104；SN65LVDS10x 4-Port LVDS and 4-Port TTL-to-LVDS Repeaters

1 Features 1• Receiver and Drivers Meet or Exceed the Requirements of ANSI EIA/TIA-644 Standard – SN65LVDS105 Receives Low-Voltage TTL (LVTTL) Levels – SN65LVDS104 Receives Differential Input Levels, ±100 mV • Typical Data Signaling Rates to 400 Mbps or Clock Frequencies to 400 MHz • Oper

丝印代码：LVDS104；SN65LVDS10x 4-Port LVDS and 4-Port TTL-to-LVDS Repeaters

1 Features 1• Receiver and Drivers Meet or Exceed the Requirements of ANSI EIA/TIA-644 Standard – SN65LVDS105 Receives Low-Voltage TTL (LVTTL) Levels – SN65LVDS104 Receives Differential Input Levels, ±100 mV • Typical Data Signaling Rates to 400 Mbps or Clock Frequencies to 400 MHz • Oper

丝印代码：LVDS104；SN65LVDS10x 4-Port LVDS and 4-Port TTL-to-LVDS Repeaters

1 Features 1• Receiver and Drivers Meet or Exceed the Requirements of ANSI EIA/TIA-644 Standard – SN65LVDS105 Receives Low-Voltage TTL (LVTTL) Levels – SN65LVDS104 Receives Differential Input Levels, ±100 mV • Typical Data Signaling Rates to 400 Mbps or Clock Frequencies to 400 MHz • Oper

丝印代码：LVDS104；SN65LVDS10x 4-Port LVDS and 4-Port TTL-to-LVDS Repeaters

1 Features 1• Receiver and Drivers Meet or Exceed the Requirements of ANSI EIA/TIA-644 Standard – SN65LVDS105 Receives Low-Voltage TTL (LVTTL) Levels – SN65LVDS104 Receives Differential Input Levels, ±100 mV • Typical Data Signaling Rates to 400 Mbps or Clock Frequencies to 400 MHz • Oper

丝印代码：LVDS104；SN65LVDS10x 4-Port LVDS and 4-Port TTL-to-LVDS Repeaters

1 Features 1• Receiver and Drivers Meet or Exceed the Requirements of ANSI EIA/TIA-644 Standard – SN65LVDS105 Receives Low-Voltage TTL (LVTTL) Levels – SN65LVDS104 Receives Differential Input Levels, ±100 mV • Typical Data Signaling Rates to 400 Mbps or Clock Frequencies to 400 MHz • Oper

丝印代码：LVDS105；SN65LVDS10x 4-Port LVDS and 4-Port TTL-to-LVDS Repeaters

1 Features 1• Receiver and Drivers Meet or Exceed the Requirements of ANSI EIA/TIA-644 Standard – SN65LVDS105 Receives Low-Voltage TTL (LVTTL) Levels – SN65LVDS104 Receives Differential Input Levels, ±100 mV • Typical Data Signaling Rates to 400 Mbps or Clock Frequencies to 400 MHz • Oper

丝印代码：LVDS105；SN65LVDS10x 4-Port LVDS and 4-Port TTL-to-LVDS Repeaters

1 Features 1• Receiver and Drivers Meet or Exceed the Requirements of ANSI EIA/TIA-644 Standard – SN65LVDS105 Receives Low-Voltage TTL (LVTTL) Levels – SN65LVDS104 Receives Differential Input Levels, ±100 mV • Typical Data Signaling Rates to 400 Mbps or Clock Frequencies to 400 MHz • Oper

丝印代码：LVDS105；SN65LVDS10x 4-Port LVDS and 4-Port TTL-to-LVDS Repeaters

1 Features 1• Receiver and Drivers Meet or Exceed the Requirements of ANSI EIA/TIA-644 Standard – SN65LVDS105 Receives Low-Voltage TTL (LVTTL) Levels – SN65LVDS104 Receives Differential Input Levels, ±100 mV • Typical Data Signaling Rates to 400 Mbps or Clock Frequencies to 400 MHz • Oper

丝印代码：LVDS105；SN65LVDS10x 4-Port LVDS and 4-Port TTL-to-LVDS Repeaters

1 Features 1• Receiver and Drivers Meet or Exceed the Requirements of ANSI EIA/TIA-644 Standard – SN65LVDS105 Receives Low-Voltage TTL (LVTTL) Levels – SN65LVDS104 Receives Differential Input Levels, ±100 mV • Typical Data Signaling Rates to 400 Mbps or Clock Frequencies to 400 MHz • Oper

丝印代码：LVDS105；SN65LVDS10x 4-Port LVDS and 4-Port TTL-to-LVDS Repeaters

1 Features 1• Receiver and Drivers Meet or Exceed the Requirements of ANSI EIA/TIA-644 Standard – SN65LVDS105 Receives Low-Voltage TTL (LVTTL) Levels – SN65LVDS104 Receives Differential Input Levels, ±100 mV • Typical Data Signaling Rates to 400 Mbps or Clock Frequencies to 400 MHz • Oper

丝印代码：LVDS105；SN65LVDS10x 4-Port LVDS and 4-Port TTL-to-LVDS Repeaters

1 Features 1• Receiver and Drivers Meet or Exceed the Requirements of ANSI EIA/TIA-644 Standard – SN65LVDS105 Receives Low-Voltage TTL (LVTTL) Levels – SN65LVDS104 Receives Differential Input Levels, ±100 mV • Typical Data Signaling Rates to 400 Mbps or Clock Frequencies to 400 MHz • Oper

丝印代码：LVDS105；SN65LVDS10x 4-Port LVDS and 4-Port TTL-to-LVDS Repeaters

1 Features 1• Receiver and Drivers Meet or Exceed the Requirements of ANSI EIA/TIA-644 Standard – SN65LVDS105 Receives Low-Voltage TTL (LVTTL) Levels – SN65LVDS104 Receives Differential Input Levels, ±100 mV • Typical Data Signaling Rates to 400 Mbps or Clock Frequencies to 400 MHz • Oper

丝印代码：LVDS105；SN65LVDS10x 4-Port LVDS and 4-Port TTL-to-LVDS Repeaters

1 Features 1• Receiver and Drivers Meet or Exceed the Requirements of ANSI EIA/TIA-644 Standard – SN65LVDS105 Receives Low-Voltage TTL (LVTTL) Levels – SN65LVDS104 Receives Differential Input Levels, ±100 mV • Typical Data Signaling Rates to 400 Mbps or Clock Frequencies to 400 MHz • Oper

丝印代码：LVDS105；SN65LVDS10x 4-Port LVDS and 4-Port TTL-to-LVDS Repeaters

1 Features 1• Receiver and Drivers Meet or Exceed the Requirements of ANSI EIA/TIA-644 Standard – SN65LVDS105 Receives Low-Voltage TTL (LVTTL) Levels – SN65LVDS104 Receives Differential Input Levels, ±100 mV • Typical Data Signaling Rates to 400 Mbps or Clock Frequencies to 400 MHz • Oper

丝印代码：LVDS108；8-PORT LVDS REPEATER

FEATURES · One Line Receiver and Eight Line Drivers Configured as an 8-Port LVDS Repeater · Line Receiver and Line Drivers Meet or Exceed the Requirements of ANSI EIA/TIA-644 Standard · Typical Data Signaling Rates to 400 Mbps or Clock Frequencies to 400 MHz · Enabling Logic Allows Individ

丝印代码：LVDS108；8-PORT LVDS REPEATER

FEATURES · One Line Receiver and Eight Line Drivers Configured as an 8-Port LVDS Repeater · Line Receiver and Line Drivers Meet or Exceed the Requirements of ANSI EIA/TIA-644 Standard · Typical Data Signaling Rates to 400 Mbps or Clock Frequencies to 400 MHz · Enabling Logic Allows Individ

丝印代码：LVDS108；8-PORT LVDS REPEATER

FEATURES · One Line Receiver and Eight Line Drivers Configured as an 8-Port LVDS Repeater · Line Receiver and Line Drivers Meet or Exceed the Requirements of ANSI EIA/TIA-644 Standard · Typical Data Signaling Rates to 400 Mbps or Clock Frequencies to 400 MHz · Enabling Logic Allows Individ

丝印代码：LVDS108；8-PORT LVDS REPEATER

FEATURES · One Line Receiver and Eight Line Drivers Configured as an 8-Port LVDS Repeater · Line Receiver and Line Drivers Meet or Exceed the Requirements of ANSI EIA/TIA-644 Standard · Typical Data Signaling Rates to 400 Mbps or Clock Frequencies to 400 MHz · Enabling Logic Allows Individ

丝印代码：LVDS108；8-PORT LVDS REPEATER

FEATURES · One Line Receiver and Eight Line Drivers Configured as an 8-Port LVDS Repeater · Line Receiver and Line Drivers Meet or Exceed the Requirements of ANSI EIA/TIA-644 Standard · Typical Data Signaling Rates to 400 Mbps or Clock Frequencies to 400 MHz · Enabling Logic Allows Individ

丝印代码：LVDS108；8-PORT LVDS REPEATER

FEATURES · One Line Receiver and Eight Line Drivers Configured as an 8-Port LVDS Repeater · Line Receiver and Line Drivers Meet or Exceed the Requirements of ANSI EIA/TIA-644 Standard · Typical Data Signaling Rates to 400 Mbps or Clock Frequencies to 400 MHz · Enabling Logic Allows Individ

丝印代码：LVDS109；DUAL 4-PORT AND DUAL 8-PORT LVDS REPEATERS

FEATURES · Two Line Receivers and Eight ('109) or Sixteen ('117) Line Drivers Meet or Exceed the Requirements of ANSI EIA/TIA-644 Standard · Typical Data Signaling Rates to 400 Mbps or Clock Frequencies to 400 MHz · Outputs Arranged in Pairs From Each Bank · Enabling Logic Allows Individual

丝印代码：LVDS109；DUAL 4-PORT AND DUAL 8-PORT LVDS REPEATERS

FEATURES · Two Line Receivers and Eight ('109) or Sixteen ('117) Line Drivers Meet or Exceed the Requirements of ANSI EIA/TIA-644 Standard · Typical Data Signaling Rates to 400 Mbps or Clock Frequencies to 400 MHz · Outputs Arranged in Pairs From Each Bank · Enabling Logic Allows Individual

丝印代码：LVDS116；16-PORT LVDS REPEATER

FEATURES · One Receiver and Sixteen Line Drivers Meet or Exceed the Requirements of ANSI EIA/TIA-644 Standard · Typical Data Signaling Rates to 400 Mbps or Clock Frequencies to 400 MHz · Enabling Logic Allows Separate Control of Each Bank of Four Channels or 2-Bit Selection of Any One of t

丝印代码：LVDS116；16-PORT LVDS REPEATER

FEATURES · One Receiver and Sixteen Line Drivers Meet or Exceed the Requirements of ANSI EIA/TIA-644 Standard · Typical Data Signaling Rates to 400 Mbps or Clock Frequencies to 400 MHz · Enabling Logic Allows Separate Control of Each Bank of Four Channels or 2-Bit Selection of Any One of t

丝印代码：LVDS116；16-PORT LVDS REPEATER

FEATURES · One Receiver and Sixteen Line Drivers Meet or Exceed the Requirements of ANSI EIA/TIA-644 Standard · Typical Data Signaling Rates to 400 Mbps or Clock Frequencies to 400 MHz · Enabling Logic Allows Separate Control of Each Bank of Four Channels or 2-Bit Selection of Any One of t

丝印代码：LVDS116；16-PORT LVDS REPEATER

FEATURES · One Receiver and Sixteen Line Drivers Meet or Exceed the Requirements of ANSI EIA/TIA-644 Standard · Typical Data Signaling Rates to 400 Mbps or Clock Frequencies to 400 MHz · Enabling Logic Allows Separate Control of Each Bank of Four Channels or 2-Bit Selection of Any One of t

丝印代码：LVDS116；16-PORT LVDS REPEATER

FEATURES · One Receiver and Sixteen Line Drivers Meet or Exceed the Requirements of ANSI EIA/TIA-644 Standard · Typical Data Signaling Rates to 400 Mbps or Clock Frequencies to 400 MHz · Enabling Logic Allows Separate Control of Each Bank of Four Channels or 2-Bit Selection of Any One of t

丝印代码：LVDS117；DUAL 4-PORT AND DUAL 8-PORT LVDS REPEATERS

FEATURES · Two Line Receivers and Eight ('109) or Sixteen ('117) Line Drivers Meet or Exceed the Requirements of ANSI EIA/TIA-644 Standard · Typical Data Signaling Rates to 400 Mbps or Clock Frequencies to 400 MHz · Outputs Arranged in Pairs From Each Bank · Enabling Logic Allows Individual

丝印代码：LVDS117；DUAL 4-PORT AND DUAL 8-PORT LVDS REPEATERS

FEATURES · Two Line Receivers and Eight ('109) or Sixteen ('117) Line Drivers Meet or Exceed the Requirements of ANSI EIA/TIA-644 Standard · Typical Data Signaling Rates to 400 Mbps or Clock Frequencies to 400 MHz · Outputs Arranged in Pairs From Each Bank · Enabling Logic Allows Individual

丝印代码：LVDS117；DUAL 4-PORT AND DUAL 8-PORT LVDS REPEATERS

FEATURES · Two Line Receivers and Eight ('109) or Sixteen ('117) Line Drivers Meet or Exceed the Requirements of ANSI EIA/TIA-644 Standard · Typical Data Signaling Rates to 400 Mbps or Clock Frequencies to 400 MHz · Outputs Arranged in Pairs From Each Bank · Enabling Logic Allows Individual

丝印代码：LVDS117；DUAL 4-PORT AND DUAL 8-PORT LVDS REPEATERS

FEATURES · Two Line Receivers and Eight ('109) or Sixteen ('117) Line Drivers Meet or Exceed the Requirements of ANSI EIA/TIA-644 Standard · Typical Data Signaling Rates to 400 Mbps or Clock Frequencies to 400 MHz · Outputs Arranged in Pairs From Each Bank · Enabling Logic Allows Individual