128K X 8 BIT 3.3V HIGH SPEED CENTER POWER CMOS SRAM

General Description The LP61L1008 is a high speed 1,048,576-bit static random access memory organized as 131,072 words by 8 bits and operates on a single 3.3V power supply. Inputs and three-state outputs are TTL compatible and allow for direct interfacing with common system bus structures. The

128K X 8 BIT 3.3V HIGH SPEED CENTER POWER CMOS SRAM

128K X 8 BIT 3.3V HIGH SPEED CENTER POWER CMOS SRAM

General Description The LP61L1008A is a high speed 1,048,576-bit static random access memory organized as 131,072 words by 8 bits and operates on a single 3.3V power supply. Inputs and three-state outputs are TTL compatible and allow for direct interfacing with common system bus structures. The

128K X 8 BIT 3.3V HIGH SPEED CENTER POWER CMOS SRAM

General Description The LP61L1008A is a high speed 1,048,576-bit static random access memory organized as 131,072 words by 8 bits and operates on a single 3.3V power supply. Inputs and three-state outputs are TTL compatible and allow for direct interfacing with common system bus structures. The

128K X 8 BIT 3.3V HIGH SPEED CENTER POWER CMOS SRAM

General Description The LP61L1008A is a high speed 1,048,576-bit static random access memory organized as 131,072 words by 8 bits and operates on a single 3.3V power supply. Inputs and three-state outputs are TTL compatible and allow for direct interfacing with common system bus structures. The

128K X 8 BIT 3.3V HIGH SPEED CENTER POWER CMOS SRAM

General Description The LP61L1008A is a high speed 1,048,576-bit static random access memory organized as 131,072 words by 8 bits and operates on a single 3.3V power supply. Inputs and three-state outputs are TTL compatible and allow for direct interfacing with common system bus structures. The

128K X 8 BIT 3.3V HIGH SPEED CENTER POWER CMOS SRAM

General Description The LP61L1008 is a high speed 1,048,576-bit static random access memory organized as 131,072 words by 8 bits and operates on a single 3.3V power supply. Inputs and three-state outputs are TTL compatible and allow for direct interfacing with common system bus structures. The

128K X 8 BIT 3.3V HIGH SPEED CENTER POWER CMOS SRAM

General Description The LP61L1008 is a high speed 1,048,576-bit static random access memory organized as 131,072 words by 8 bits and operates on a single 3.3V power supply. Inputs and three-state outputs are TTL compatible and allow for direct interfacing with common system bus structures. The

128K X 8 BIT 3.3V HIGH SPEED CENTER POWER CMOS SRAM

General Description The LP61L1008 is a high speed 1,048,576-bit static random access memory organized as 131,072 words by 8 bits and operates on a single 3.3V power supply. Inputs and three-state outputs are TTL compatible and allow for direct interfacing with common system bus structures. The

128K X 8 BIT 3.3V HIGH SPEED CENTER POWER CMOS SRAM

General Description The LP61L1008 is a high speed 1,048,576-bit static random access memory organized as 131,072 words by 8 bits and operates on a single 3.3V power supply. Inputs and three-state outputs are TTL compatible and allow for direct interfacing with common system bus structures. The

128K X 8 BIT 3.3V HIGH SPEED CENTER POWER CMOS SRAM