位置：首页 > IC中文资料第6409页 > K4H560438D
| 型号 | 功能描述 | 生产厂家 企业 | LOGO | 操作 |
|---|---|---|---|---|
128Mb DDR SDRAM Features • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe(DQS) • Four banks operation • Differential clock inputs(CK and CK) • DLL aligns DQ and DQS transition with CK transition • MRS cycle with address key programs -. Read latency 2, 2.5 ( | Samsung 三星 |   | ||
128Mb DDR SDRAM Features • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe(DQS) • Four banks operation • Differential clock inputs(CK and CK) • DLL aligns DQ and DQS transition with CK transition • MRS cycle with address key programs -. Read latency 2, 2.5 ( | Samsung 三星 | | ||
128Mb DDR SDRAM Features • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe(DQS) • Four banks operation • Differential clock inputs(CK and CK) • DLL aligns DQ and DQS transition with CK transition • MRS cycle with address key programs -. Read latency 2, 2.5 ( | Samsung 三星 | | ||
128Mb DDR SDRAM Features • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe(DQS) • Four banks operation • Differential clock inputs(CK and CK) • DLL aligns DQ and DQS transition with CK transition • MRS cycle with address key programs -. Read latency 2, 2.5 ( | Samsung 三星 | | ||
128Mb DDR SDRAM Features • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe(DQS) • Four banks operation • Differential clock inputs(CK and CK) • DLL aligns DQ and DQS transition with CK transition • MRS cycle with address key programs -. Read latency 2, 2.5 ( | Samsung 三星 | | ||
128Mb DDR SDRAM Features • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe(DQS) • Four banks operation • Differential clock inputs(CK and CK) • DLL aligns DQ and DQS transition with CK transition • MRS cycle with address key programs -. Read latency 2, 2.5 ( | Samsung 三星 | | ||
128Mb DDR SDRAM Features • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe(DQS) • Four banks operation • Differential clock inputs(CK and CK) • DLL aligns DQ and DQS transition with CK transition • MRS cycle with address key programs -. Read latency 2, 2.5 ( | Samsung 三星 | | ||
DDR 256Mb | Samsung 三星 | | ||
DDR 256Mb 文件：291.04 Kbytes Page：26 Pages | Samsung 三星 | | ||
DDR 256Mb 文件：291.04 Kbytes Page：26 Pages | Samsung 三星 | | ||
DDR 256Mb 文件：291.04 Kbytes Page：26 Pages | Samsung 三星 | | ||
DDR 256Mb 文件：291.04 Kbytes Page：26 Pages | Samsung 三星 | | ||
DDR 256Mb 文件：291.04 Kbytes Page：26 Pages | Samsung 三星 | | ||
DDR 256Mb 文件：291.04 Kbytes Page：26 Pages | Samsung 三星 | | ||
DDR 256Mb 文件：291.04 Kbytes Page：26 Pages | Samsung 三星 | | ||
256Mb sTSOPII | Samsung 三星 | | ||
256Mb sTSOPII 文件：91.5 Kbytes Page：18 Pages | Samsung 三星 | | ||
256Mb sTSOPII 文件：91.5 Kbytes Page：18 Pages | Samsung 三星 | | ||
256Mb sTSOPII 文件：91.5 Kbytes Page：18 Pages | Samsung 三星 | | ||
256Mb sTSOPII 文件：91.5 Kbytes Page：18 Pages | Samsung 三星 | | ||
256Mb sTSOPII 文件：91.5 Kbytes Page：18 Pages | Samsung 三星 | | ||
256Mb sTSOPII 文件：91.5 Kbytes Page：18 Pages | Samsung 三星 | | ||
256Mb sTSOPII 文件：91.5 Kbytes Page：18 Pages | Samsung 三星 | | ||
256Mb sTSOPII 文件：91.5 Kbytes Page：18 Pages | Samsung 三星 | | ||
256Mb sTSOPII 文件：91.5 Kbytes Page：18 Pages | Samsung 三星 | | ||
256Mb | Samsung 三星 | | ||
256Mb 文件：235.33 Kbytes Page：25 Pages | Samsung 三星 | | ||
256Mb 文件：235.33 Kbytes Page：25 Pages | Samsung 三星 | | ||
256Mb 文件：235.33 Kbytes Page：25 Pages | Samsung 三星 | | ||
256Mb 文件：235.33 Kbytes Page：25 Pages | Samsung 三星 | | ||
256Mb 文件：235.33 Kbytes Page：25 Pages | Samsung 三星 | | ||
256Mb 文件：235.33 Kbytes Page：25 Pages | Samsung 三星 | | ||
256Mb 文件：235.33 Kbytes Page：25 Pages | Samsung 三星 | | ||
256Mb 文件：235.33 Kbytes Page：25 Pages | Samsung 三星 | | ||
256Mb 文件：235.33 Kbytes Page：25 Pages | Samsung 三星 | | ||
256Mb E-die DDR SDRAM Specification 60Ball FBGA (x4/x8) 文件：244.04 Kbytes Page：24 Pages | Samsung 三星 | |
K4H560438D产品属性
- 类型
描述
- 型号
K4H560438D
- 制造商
SAMSUNG
- 制造商全称
Samsung semiconductor
- 功能描述
DDR 256Mb
| IC供应商 | 芯片型号 | 品牌 | 批号 | 封装 | 库存 | 备注 | 价格 |
|---|---|---|---|---|---|---|---|
SAMSUNG/三星 |
24+ |
NA/ |
3516 |
原装现货,当天可交货,原型号开票 |
|||
SAMSUNG |
24+ |
TSSOP |
20000 |
全新原厂原装，进口正品现货，正规渠道可含税！！ |
|||
SAM |
24+/25+ |
480 |
原装正品现货库存价优 |
||||
SAMSUNG |
2025+ |
TSOP |
4365 |
全新原厂原装产品、公司现货销售 |
|||
SAMSUNG/三星 |
22+ |
TSOP |
12245 |
现货,原厂原装假一罚十! |
|||
SAMSUNG/三星 |
原厂封装 |
9800 |
原装进口公司现货假一赔百 |
||||
SAMSUNG/三星 |
25+ |
NA |
880000 |
明嘉莱只做原装正品现货 |
|||
SAMSUN |
25+ |
TSOP |
383 |
百分百原装正品 真实公司现货库存 本公司只做原装 可 |
|||
SAMSUNG |
16+ |
QFP |
4000 |
进口原装现货/价格优势! |
|||
Samsung |
NA |
8560 |
一级代理 原装正品假一罚十价格优势长期供货 |
K4H560438D规格书下载地址
K4H560438D参数引脚图相关
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- K4H560438D-GCA2
- K4H560438D-GC
- K4H560438C-TLB0
- K4H560438C-TLA2
- K4H560438C-TLA0
- K4H560438C-TCB0
- K4H560438C-TCA2
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- K4H560438B-TLB0
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- K4H560438A-TLB0
- K4H560438A-TLA2
- K4H560438A-TLA0
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- K4H560438A-TCA0
- K4H560438
- K4H56038D-TC
- K4-GALI
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- K4107
- K4101
K4H560438D数据表相关新闻
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2019-10-28
DdatasheetPDF页码索引
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