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型号	功能描述	生产厂家&企业	LOGO
K4H560438	128Mb DDR SDRAM Features • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe(DQS) • Four banks operation • Differential clock inputs(CK and CK) • DLL aligns DQ and DQS transition with CK transition • MRS cycle with address key programs -. Read latency 2, 2.5 (	Samsung 三星	Samsung
K4H560438A-TCA0	128Mb DDR SDRAM Features • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe(DQS) • Four banks operation • Differential clock inputs(CK and CK) • DLL aligns DQ and DQS transition with CK transition • MRS cycle with address key programs -. Read latency 2, 2.5 (	Samsung 三星	Samsung
K4H560438A-TCA2	128Mb DDR SDRAM Features • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe(DQS) • Four banks operation • Differential clock inputs(CK and CK) • DLL aligns DQ and DQS transition with CK transition • MRS cycle with address key programs -. Read latency 2, 2.5 (	Samsung 三星	Samsung
K4H560438A-TCB0	128Mb DDR SDRAM Features • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe(DQS) • Four banks operation • Differential clock inputs(CK and CK) • DLL aligns DQ and DQS transition with CK transition • MRS cycle with address key programs -. Read latency 2, 2.5 (	Samsung 三星	Samsung
K4H560438A-TLA0	128Mb DDR SDRAM Features • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe(DQS) • Four banks operation • Differential clock inputs(CK and CK) • DLL aligns DQ and DQS transition with CK transition • MRS cycle with address key programs -. Read latency 2, 2.5 (	Samsung 三星	Samsung
K4H560438A-TLA2	128Mb DDR SDRAM Features • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe(DQS) • Four banks operation • Differential clock inputs(CK and CK) • DLL aligns DQ and DQS transition with CK transition • MRS cycle with address key programs -. Read latency 2, 2.5 (	Samsung 三星	Samsung
K4H560438A-TLB0	128Mb DDR SDRAM Features • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe(DQS) • Four banks operation • Differential clock inputs(CK and CK) • DLL aligns DQ and DQS transition with CK transition • MRS cycle with address key programs -. Read latency 2, 2.5 (	Samsung 三星	Samsung
K4H560438B-TCA0	128Mb DDR SDRAM Features • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe(DQS) • Four banks operation • Differential clock inputs(CK and CK) • DLL aligns DQ and DQS transition with CK transition • MRS cycle with address key programs -. Read latency 2, 2.5 (	Samsung 三星	Samsung
K4H560438B-TCA2	128Mb DDR SDRAM Features • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe(DQS) • Four banks operation • Differential clock inputs(CK and CK) • DLL aligns DQ and DQS transition with CK transition • MRS cycle with address key programs -. Read latency 2, 2.5 (	Samsung 三星	Samsung
K4H560438B-TCB0	128Mb DDR SDRAM Features • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe(DQS) • Four banks operation • Differential clock inputs(CK and CK) • DLL aligns DQ and DQS transition with CK transition • MRS cycle with address key programs -. Read latency 2, 2.5 (	Samsung 三星	Samsung
K4H560438B-TLA0	128Mb DDR SDRAM Features • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe(DQS) • Four banks operation • Differential clock inputs(CK and CK) • DLL aligns DQ and DQS transition with CK transition • MRS cycle with address key programs -. Read latency 2, 2.5 (	Samsung 三星	Samsung
K4H560438B-TLA2	128Mb DDR SDRAM Features • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe(DQS) • Four banks operation • Differential clock inputs(CK and CK) • DLL aligns DQ and DQS transition with CK transition • MRS cycle with address key programs -. Read latency 2, 2.5 (	Samsung 三星	Samsung
K4H560438B-TLB0	128Mb DDR SDRAM Features • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe(DQS) • Four banks operation • Differential clock inputs(CK and CK) • DLL aligns DQ and DQS transition with CK transition • MRS cycle with address key programs -. Read latency 2, 2.5 (	Samsung 三星	Samsung
K4H560438C-TCA0	128Mb DDR SDRAM Features • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe(DQS) • Four banks operation • Differential clock inputs(CK and CK) • DLL aligns DQ and DQS transition with CK transition • MRS cycle with address key programs -. Read latency 2, 2.5 (	Samsung 三星	Samsung
K4H560438C-TCA2	128Mb DDR SDRAM Features • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe(DQS) • Four banks operation • Differential clock inputs(CK and CK) • DLL aligns DQ and DQS transition with CK transition • MRS cycle with address key programs -. Read latency 2, 2.5 (	Samsung 三星	Samsung
K4H560438C-TCB0	128Mb DDR SDRAM Features • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe(DQS) • Four banks operation • Differential clock inputs(CK and CK) • DLL aligns DQ and DQS transition with CK transition • MRS cycle with address key programs -. Read latency 2, 2.5 (	Samsung 三星	Samsung
K4H560438C-TLA0	128Mb DDR SDRAM Features • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe(DQS) • Four banks operation • Differential clock inputs(CK and CK) • DLL aligns DQ and DQS transition with CK transition • MRS cycle with address key programs -. Read latency 2, 2.5 (	Samsung 三星	Samsung
K4H560438C-TLA2	128Mb DDR SDRAM Features • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe(DQS) • Four banks operation • Differential clock inputs(CK and CK) • DLL aligns DQ and DQS transition with CK transition • MRS cycle with address key programs -. Read latency 2, 2.5 (	Samsung 三星	Samsung
K4H560438C-TLB0	128Mb DDR SDRAM Features • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe(DQS) • Four banks operation • Differential clock inputs(CK and CK) • DLL aligns DQ and DQS transition with CK transition • MRS cycle with address key programs -. Read latency 2, 2.5 (	Samsung 三星	Samsung
K4H560438D-TCA0	128Mb DDR SDRAM Features • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe(DQS) • Four banks operation • Differential clock inputs(CK and CK) • DLL aligns DQ and DQS transition with CK transition • MRS cycle with address key programs -. Read latency 2, 2.5 (	Samsung 三星	Samsung
K4H560438D-TCA2	128Mb DDR SDRAM Features • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe(DQS) • Four banks operation • Differential clock inputs(CK and CK) • DLL aligns DQ and DQS transition with CK transition • MRS cycle with address key programs -. Read latency 2, 2.5 (	Samsung 三星	Samsung
K4H560438D-TCB0	128Mb DDR SDRAM Features • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe(DQS) • Four banks operation • Differential clock inputs(CK and CK) • DLL aligns DQ and DQS transition with CK transition • MRS cycle with address key programs -. Read latency 2, 2.5 (	Samsung 三星	Samsung
K4H560438D-TLA0	128Mb DDR SDRAM Features • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe(DQS) • Four banks operation • Differential clock inputs(CK and CK) • DLL aligns DQ and DQS transition with CK transition • MRS cycle with address key programs -. Read latency 2, 2.5 (	Samsung 三星	Samsung
K4H560438D-TLA2	128Mb DDR SDRAM Features • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe(DQS) • Four banks operation • Differential clock inputs(CK and CK) • DLL aligns DQ and DQS transition with CK transition • MRS cycle with address key programs -. Read latency 2, 2.5 (	Samsung 三星	Samsung
K4H560438D-TLB0	128Mb DDR SDRAM Features • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe(DQS) • Four banks operation • Differential clock inputs(CK and CK) • DLL aligns DQ and DQS transition with CK transition • MRS cycle with address key programs -. Read latency 2, 2.5 (	Samsung 三星	Samsung
K4H560438E-TCA0	128Mb DDR SDRAM Features • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe(DQS) • Four banks operation • Differential clock inputs(CK and CK) • DLL aligns DQ and DQS transition with CK transition • MRS cycle with address key programs -. Read latency 2, 2.5 (	Samsung 三星	Samsung
K4H560438E-TCA2	128Mb DDR SDRAM Features • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe(DQS) • Four banks operation • Differential clock inputs(CK and CK) • DLL aligns DQ and DQS transition with CK transition • MRS cycle with address key programs -. Read latency 2, 2.5 (	Samsung 三星	Samsung
K4H560438E-TCB0	128Mb DDR SDRAM Features • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe(DQS) • Four banks operation • Differential clock inputs(CK and CK) • DLL aligns DQ and DQS transition with CK transition • MRS cycle with address key programs -. Read latency 2, 2.5 (	Samsung 三星	Samsung
K4H560438E-TLA0	128Mb DDR SDRAM Features • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe(DQS) • Four banks operation • Differential clock inputs(CK and CK) • DLL aligns DQ and DQS transition with CK transition • MRS cycle with address key programs -. Read latency 2, 2.5 (	Samsung 三星	Samsung
K4H560438E-TLA2	128Mb DDR SDRAM Features • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe(DQS) • Four banks operation • Differential clock inputs(CK and CK) • DLL aligns DQ and DQS transition with CK transition • MRS cycle with address key programs -. Read latency 2, 2.5 (	Samsung 三星	Samsung
K4H560438E-TLB0	128Mb DDR SDRAM Features • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe(DQS) • Four banks operation • Differential clock inputs(CK and CK) • DLL aligns DQ and DQS transition with CK transition • MRS cycle with address key programs -. Read latency 2, 2.5 (	Samsung 三星	Samsung
K4H560438H	DDR SDRAM Product Guide Consumer Memory	Samsung 三星	Samsung
K4H560438J	Consumer Memory SDRAM Product Guide Memory Division November 2007	Samsung 三星	Samsung
K4H560438J	DDR SDRAM Product Guide Consumer Memory	Samsung 三星	Samsung
K4H560438J	256Mb J-die DDR SDRAM Specification Consumer Memory	Samsung 三星	Samsung
K4H560438J-LC/LB0	256Mb J-die DDR SDRAM Specification Consumer Memory	Samsung 三星	Samsung
K4H560438J-LC/LB3	256Mb J-die DDR SDRAM Specification Consumer Memory	Samsung 三星	Samsung
K4H560438J-LCSLASHLB0	256Mb J-die DDR SDRAM Specification Consumer Memory	Samsung 三星	Samsung
K4H560438J-LCSLASHLB3	256Mb J-die DDR SDRAM Specification Consumer Memory	Samsung 三星	Samsung
K4H560438M-TCA0	128Mb DDR SDRAM Features • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe(DQS) • Four banks operation • Differential clock inputs(CK and CK) • DLL aligns DQ and DQS transition with CK transition • MRS cycle with address key programs -. Read latency 2, 2.5 (	Samsung 三星	Samsung
K4H560438M-TCA2	128Mb DDR SDRAM Features • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe(DQS) • Four banks operation • Differential clock inputs(CK and CK) • DLL aligns DQ and DQS transition with CK transition • MRS cycle with address key programs -. Read latency 2, 2.5 (	Samsung 三星	Samsung
K4H560438M-TCB0	128Mb DDR SDRAM Features • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe(DQS) • Four banks operation • Differential clock inputs(CK and CK) • DLL aligns DQ and DQS transition with CK transition • MRS cycle with address key programs -. Read latency 2, 2.5 (	Samsung 三星	Samsung
K4H560438M-TLA0	128Mb DDR SDRAM Features • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe(DQS) • Four banks operation • Differential clock inputs(CK and CK) • DLL aligns DQ and DQS transition with CK transition • MRS cycle with address key programs -. Read latency 2, 2.5 (	Samsung 三星	Samsung
K4H560438M-TLA2	128Mb DDR SDRAM Features • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe(DQS) • Four banks operation • Differential clock inputs(CK and CK) • DLL aligns DQ and DQS transition with CK transition • MRS cycle with address key programs -. Read latency 2, 2.5 (	Samsung 三星	Samsung
K4H560438M-TLB0	128Mb DDR SDRAM Features • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe(DQS) • Four banks operation • Differential clock inputs(CK and CK) • DLL aligns DQ and DQS transition with CK transition • MRS cycle with address key programs -. Read latency 2, 2.5 (	Samsung 三星	Samsung
K4H560438N	Consumer Memory SDRAM Product Guide Memory Division November 2007	Samsung 三星	Samsung
K4H560438D-GC	DDR 256Mb 文件：291.04 Kbytes Page：26 Pages	Samsung 三星	Samsung
K4H560438D-GCA2	DDR 256Mb 文件：291.04 Kbytes Page：26 Pages	Samsung 三星	Samsung
K4H560438D-GCB0	DDR 256Mb 文件：291.04 Kbytes Page：26 Pages	Samsung 三星	Samsung
K4H560438D-GCB3	DDR 256Mb 文件：291.04 Kbytes Page：26 Pages	Samsung 三星	Samsung
K4H560438D-GLA2	DDR 256Mb 文件：291.04 Kbytes Page：26 Pages	Samsung 三星	Samsung
K4H560438D-GLB0	DDR 256Mb 文件：291.04 Kbytes Page：26 Pages	Samsung 三星	Samsung
K4H560438D-GLB3	DDR 256Mb 文件：291.04 Kbytes Page：26 Pages	Samsung 三星	Samsung
K4H560438D-NC	256Mb sTSOPII 文件：91.5 Kbytes Page：18 Pages	Samsung 三星	Samsung
K4H560438D-NC/LA0	256Mb sTSOPII 文件：91.5 Kbytes Page：18 Pages	Samsung 三星	Samsung
K4H560438D-NC/LA2	256Mb sTSOPII 文件：91.5 Kbytes Page：18 Pages	Samsung 三星	Samsung
K4H560438D-NC/LB0	256Mb sTSOPII 文件：91.5 Kbytes Page：18 Pages	Samsung 三星	Samsung
K4H560438D-NC/LB3	256Mb sTSOPII 文件：91.5 Kbytes Page：18 Pages	Samsung 三星	Samsung
K4H560438D-NCSLASHLA0	256Mb sTSOPII 文件：91.5 Kbytes Page：18 Pages	Samsung 三星	Samsung
K4H560438D-NCSLASHLA2	256Mb sTSOPII 文件：91.5 Kbytes Page：18 Pages	Samsung 三星	Samsung

K4H560438产品属性

类型
描述
型号
K4H560438
制造商
SAMSUNG
制造商全称
Samsung semiconductor
功能描述
128Mb DDR SDRAM

K4H560438供应商更多...

更新时间：2025-8-6 23:00:00

IC供应商	芯片型号	品牌	批号	封装	库存	备注	价格
深圳市得捷芯城科技有限公司	K4H560438E-TCB0	SAMSUNG/三星	24+	NA/	3516	原装现货,当天可交货,原型号开票	询价
深圳市纳艾斯科技有限公司	K4H560438E-TCB0	SAMSUNG/三星	24+	NA	80000	只做自己库存全新原装进口正品假一赔百可开13%增	询价
深圳市明嘉莱科技有限公司	K4H560438C-TCA2	SAMSUNG/三星	25+	NA	880000	明嘉莱只做原装正品现货	询价
深圳市华睿芯科技有限公司	K4H560438E-TCBO	SAMSUNG	24+	TSSOP	20000	全新原厂原装，进口正品现货，正规渠道可含税！！	询价
深圳市联世界科技有限公司	K4H560438BTCBO	SAM	24+/25+		480	原装正品现货库存价优	询价
深圳市威雅利发展有限公司	K4H560438E-TCB3	SAMSUNG	0510+	TSOP66	12	一级代理,专注军工、汽车、医疗、工业、新能源、电力	询价
深圳市英卓尔科技有限公司	K4H560438E-TCB0	SAMSUNG	20+	TSOP	2960	诚信交易大量库存现货	询价
深圳市科翼源电子有限公司	K4H560438D-TCBO	三星	23+	TSSOP	2860	原厂原装正品	询价
贸泽芯城（深圳）电子科技有限公司	K4H560438H-UCB3	SAMSUNG/三星	23+	TSOP66	5000	一级代理原厂VIP渠道,专注军工、汽车、医疗、工业、	询价
深圳市赛美科科技有限公司	K4H560438D-TCB0	Samsung		NA	8560	一级代理原装正品假一罚十价格优势长期供货	询价

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K4H560438产品属性

K4H560438供应商更多...

K4H560438芯片相关品牌

K4H560438规格书下载地址

K4H560438参数引脚图相关

K4H560438数据表相关新闻

K4E6E304EB-EGCF

K4FBE3D4HB-KFC

K4F6E3S4HM-MGCJ

K4T1G164QG-BCE7 进口原装，主营军工级IC

K4S641632H-TC30，K4S641632H-UC6，K4SA160822DTC1H，K616V1002CT-12

K4T1G084QJ-BCE7

DdatasheetPDF页码索引