Dual JK Flip-Flop

Dual JK Flip-Flop The IW4027B is a Dual JK Flip-Flop which is edge-triggered and features independent Set, Reset, and Clock inputs. Data is accepted when the Clock is LOW and transferred to the output on the positivegoing edge of the Clock. The active HIGH asynchronous Reset and Set are independe

Dual JK Flip-Flop

The IW4027B is a Dual JK Flip-Flop which is edge-triggered and features independent Set, Reset, and Clock inputs. Data is accepted when the Clock is LOW and transferred to the output on the positive going edge of the Clock. The active HIGH asynchronous Reset and Set are independent and override th

Dual JK Flip-Flop

Dual JK Flip-Flop

The IW4027B is a Dual JK Flip-Flop which is edge-triggered and features independent Set, Reset, and Clock inputs. Data is accepted when the Clock is LOW and transferred to the output on the positive going edge of the Clock. The active HIGH asynchronous Reset and Set are independent and override th

Dual JK Flip-Flop

Dual JK Flip-Flop The IW4027B is a Dual JK Flip-Flop which is edge-triggered and features independent Set, Reset, and Clock inputs. Data is accepted when the Clock is LOW and transferred to the output on the positivegoing edge of the Clock. The active HIGH asynchronous Reset and Set are independe

Dual JK Flip-Flop

Dual JK Flip-Flop The IW4027B is a Dual JK Flip-Flop which is edge-triggered and features independent Set, Reset, and Clock inputs. Data is accepted when the Clock is LOW and transferred to the output on the positivegoing edge of the Clock. The active HIGH asynchronous Reset and Set are independe

Dual JK Flip-Flop

The IW4027B is a Dual JK Flip-Flop which is edge-triggered and features independent Set, Reset, and Clock inputs. Data is accepted when the Clock is LOW and transferred to the output on the positive going edge of the Clock. The active HIGH asynchronous Reset and Set are independent and override th

Dual JK Flip-Flop

Dual J-K Flip-Flop

Dual JK flip-flop

DESCRIPTION The HEF4027B is a dual JK flip-flop which is edge-triggered and features independent set direct (SD), clear direct (CD), clock (CP) inputs and outputs (O,O). Data is accepted when CP is LOW, and transferred to the output on the positive-going edge of the clock. The active HIGH as

Dual JK flip-flop

DESCRIPTION The HEF4027B is a dual JK flip-flop which is edge-triggered and features independent set direct (SD), clear direct (CD), clock (CP) inputs and outputs (O,O). Data is accepted when CP is LOW, and transferred to the output on the positive-going edge of the clock. The active HIGH as

Dual JK flip-flop

DESCRIPTION The HEF4027B is a dual JK flip-flop which is edge-triggered and features independent set direct (SD), clear direct (CD), clock (CP) inputs and outputs (O,O). Data is accepted when CP is LOW, and transferred to the output on the positive-going edge of the clock. The active HIGH as

Silicon planar type

Silicon planar type For stabilization of power supply ■ Features • High reliability, achieved by the DHD structure • Allowing to insert to a 5 mm pitch hole • Finely divided zener-voltage rank • Sharp rising performance • Wide voltage range: VZ = 2.0 V to 39 V

Silicon planar type

Silicon planar type For stabilization of power supply ■ Features • High reliability, achieved by the DHD structure • Allowing to insert to a 5 mm pitch hole • Finely divided zener-voltage rank • Sharp rising performance • Wide voltage range: VZ = 2.0 V to 39 V