Dual JK flip-flop

DESCRIPTION The HEF4027B is a dual JK flip-flop which is edge-triggered and features independent set direct (SD), clear direct (CD), clock (CP) inputs and outputs (O,O). Data is accepted when CP is LOW, and transferred to the output on the positive-going edge of the clock. The active HIGH as

DUAL-J-K MASTER-SLAVE FLIP-FLOP

DESCRIPTION The HCC4027B (extended temperature range) and HCF4027B (intermediate temperature range) are monolithic integrated circuit, available in 16-lead dual in-line plastic or ceramic package and plastic micro package. ■ SET-RESET CAPABILITY ■ STATIC FLIP-FLOP OPERATION - RETAINS

DUAL-J-K MASTER-SLAVE FLIP-FLOP

CMOS DUAL J-K MASTER-SLAVER FLIP-FLOP

文件：531 Kbytes Page：12 Pages

包装：袋 描述：LM.TR, ADJUSTABLE FEET, LEVELLIN 五金件，紧固件，配件 缓冲器，支脚，焊盘，握把

包装：袋 描述：LM.TR, ADJUSTABLE FEET, LEVELLIN 五金件，紧固件，配件 缓冲器，支脚，焊盘，握把

GERMANIUM PNP TRANSISTORS

文件：2.44311 Mbytes Page：6 Pages

3Power Dividers

文件：479.15 Kbytes Page：3 Pages

Power Dividers

文件：485.07 Kbytes Page：4 Pages

Power Dividers

文件：485.07 Kbytes Page：4 Pages

Power Dividers

文件：184.2 Kbytes Page：3 Pages

Power Dividers

文件：190.12 Kbytes Page：4 Pages

Power Dividers

文件：190.12 Kbytes Page：4 Pages

Component Carriers and Housings

文件：744.63 Kbytes Page：20 Pages

Component Carriers and Housings

文件：733.81 Kbytes Page：20 Pages

GERMANIUM PNP TRANSISTORS

文件：2.44311 Mbytes Page：6 Pages

Power Dividers

文件：206.56 Kbytes Page：4 Pages

Power Dividers

文件：200.64 Kbytes Page：3 Pages

Power Dividers

文件：206.56 Kbytes Page：4 Pages

GERMANIUM PNP TRANSISTORS

文件：2.44311 Mbytes Page：6 Pages

Power Dividers

文件：513.26 Kbytes Page：4 Pages

Power Dividers

文件：507.34 Kbytes Page：3 Pages

Power Dividers

文件：513.26 Kbytes Page：4 Pages

Bobbin Mount End Stop - Type VE (Male)

文件：76.4 Kbytes Page：1 Pages

Dual JK flip-flop

DESCRIPTION The HEF4027B is a dual JK flip-flop which is edge-triggered and features independent set direct (SD), clear direct (CD), clock (CP) inputs and outputs (O,O). Data is accepted when CP is LOW, and transferred to the output on the positive-going edge of the clock. The active HIGH as

Dual JK flip-flop

DESCRIPTION The HEF4027B is a dual JK flip-flop which is edge-triggered and features independent set direct (SD), clear direct (CD), clock (CP) inputs and outputs (O,O). Data is accepted when CP is LOW, and transferred to the output on the positive-going edge of the clock. The active HIGH as

Silicon planar type

Silicon planar type For stabilization of power supply ■ Features • High reliability, achieved by the DHD structure • Allowing to insert to a 5 mm pitch hole • Finely divided zener-voltage rank • Sharp rising performance • Wide voltage range: VZ = 2.0 V to 39 V

Silicon planar type

Silicon planar type For stabilization of power supply ■ Features • High reliability, achieved by the DHD structure • Allowing to insert to a 5 mm pitch hole • Finely divided zener-voltage rank • Sharp rising performance • Wide voltage range: VZ = 2.0 V to 39 V

CMOS DUAL J-K MASTER-SLAVER FLIP-FLOP

CMOS Dual J-K Master-Slave Flip-Flop

CMOS Dual J-K Master-Slave Flip-Flop

CMOS DUAL J-K MASTER-SLAVER FLIP-FLOP

CMOS DUAL J-K MASTER-SLAVER FLIP-FLOP

CMOS Dual J-K Master-Slave Flip-Flop

DUAL-J-K MASTER-SLAVE FLIP-FLOP

Dual J-K Flip Flop

Dual JK flip-flop

Dual JK flip-flop

Dual JK flip-flop

Dual J-K Flip-Flop

Dual J-K Flip-Flop

Dual J-K Flip-Flop

Dual J−K Flip−Flop

COMPLEMENTARY METAL OXIDE SILICON

DUAL D TYPE FUP FLOP

DUAL J-K MASTER-SLAVE FLIP FLOP

Dual J-K Master-Slave Flip Flop

DUAL J-K MASTER-SLAVE FLIP FLOP