In-System Programmable 3.3V SuperWIDE™ High Density PLD

Features • Second Generation SuperWIDE HIGH DENSITY IN-SYSTEM PROGRAMMABLE LOGIC DEVICE — 3.3V Power Supply — User Selectable 3.3V/2.5V I/O — 24000 PLD Gates / 512 Macrocells — Up to 256 I/O Pins — 512 Registers — High-Speed Global Interconnect — SuperWIDE Generic Logic Block (32 Macrocel

In-System Programmable 3.3V SuperWIDE??High Density PLD

ispLSI 5000VE Description The ispLSI 5000VE Family of In-System Programmable High Density Logic Devices is based on Generic Logic Blocks (GLBs) of 32 registered macrocells and a single Global Routing Pool (GRP) structure interconnecting the GLBs. Outputs from the GLBs drive the Global Routing Po

In-System Programmable 3.3V SuperWIDE??High Density PLD

ispLSI 5000VE Description The ispLSI 5000VE Family of In-System Programmable High Density Logic Devices is based on Generic Logic Blocks (GLBs) of 32 registered macrocells and a single Global Routing Pool (GRP) structure interconnecting the GLBs. Outputs from the GLBs drive the Global Routing Po

In-System Programmable 3.3V SuperWIDE??High Density PLD

ispLSI 5000VE Description The ispLSI 5000VE Family of In-System Programmable High Density Logic Devices is based on Generic Logic Blocks (GLBs) of 32 registered macrocells and a single Global Routing Pool (GRP) structure interconnecting the GLBs. Outputs from the GLBs drive the Global Routing Po

In-System Programmable 3.3V SuperWIDE??High Density PLD

ispLSI 5000VE Description The ispLSI 5000VE Family of In-System Programmable High Density Logic Devices is based on Generic Logic Blocks (GLBs) of 32 registered macrocells and a single Global Routing Pool (GRP) structure interconnecting the GLBs. Outputs from the GLBs drive the Global Routing Po

In-System Programmable 3.3V SuperWIDE??High Density PLD

ispLSI 5000VE Description The ispLSI 5000VE Family of In-System Programmable High Density Logic Devices is based on Generic Logic Blocks (GLBs) of 32 registered macrocells and a single Global Routing Pool (GRP) structure interconnecting the GLBs. Outputs from the GLBs drive the Global Routing Po

In-System Programmable 3.3V SuperWIDE??High Density PLD

ispLSI 5000VE Description The ispLSI 5000VE Family of In-System Programmable High Density Logic Devices is based on Generic Logic Blocks (GLBs) of 32 registered macrocells and a single Global Routing Pool (GRP) structure interconnecting the GLBs. Outputs from the GLBs drive the Global Routing Po

In-System Programmable 3.3V SuperWIDE??High Density PLD

ispLSI 5000VE Description The ispLSI 5000VE Family of In-System Programmable High Density Logic Devices is based on Generic Logic Blocks (GLBs) of 32 registered macrocells and a single Global Routing Pool (GRP) structure interconnecting the GLBs. Outputs from the GLBs drive the Global Routing Po

In-System Programmable 3.3V SuperWIDE??High Density PLD

ispLSI 5000VE Description The ispLSI 5000VE Family of In-System Programmable High Density Logic Devices is based on Generic Logic Blocks (GLBs) of 32 registered macrocells and a single Global Routing Pool (GRP) structure interconnecting the GLBs. Outputs from the GLBs drive the Global Routing Po

In-System Programmable 3.3V SuperWIDE??High Density PLD

ispLSI 5000VE Description The ispLSI 5000VE Family of In-System Programmable High Density Logic Devices is based on Generic Logic Blocks (GLBs) of 32 registered macrocells and a single Global Routing Pool (GRP) structure interconnecting the GLBs. Outputs from the GLBs drive the Global Routing Po

In-System Programmable 3.3V SuperWIDE??High Density PLD

ispLSI 5000VE Description The ispLSI 5000VE Family of In-System Programmable High Density Logic Devices is based on Generic Logic Blocks (GLBs) of 32 registered macrocells and a single Global Routing Pool (GRP) structure interconnecting the GLBs. Outputs from the GLBs drive the Global Routing Po

In-System Programmable 3.3V SuperWIDE??High Density PLD

ispLSI 5000VE Description The ispLSI 5000VE Family of In-System Programmable High Density Logic Devices is based on Generic Logic Blocks (GLBs) of 32 registered macrocells and a single Global Routing Pool (GRP) structure interconnecting the GLBs. Outputs from the GLBs drive the Global Routing Po

In-System Programmable 3.3V SuperWIDE??High Density PLD

ispLSI 5000VE Description The ispLSI 5000VE Family of In-System Programmable High Density Logic Devices is based on Generic Logic Blocks (GLBs) of 32 registered macrocells and a single Global Routing Pool (GRP) structure interconnecting the GLBs. Outputs from the GLBs drive the Global Routing Po

In-System Programmable 3.3V SuperWIDE™ High Density PLD

40-Channel, 3 V/5 V, Single-Supply, Serial, 14-Bit Voltage Output DAC

GENERAL DESCRIPTION The AD5384 is a complete single-supply, 40-channel, 14-bit digital-to-analog converter (DAC) available in a 100-ball CSP_BGA package. All 40 channels have an on-chip output amplifier with rail-to-rail operation. The AD5384 includes an internal 1.25 V/2.5 V, 10 ppm/°C reference

107 DB 24 BIT 96KHZ 4 CHANNEL ADC

GENERAL DESCRIPTION The AK5384 is a 4-channel A/D Converter with wide sampling rate of 8kHz ~ 96kHz and is suitable for Multi-channel audio system. The AK5384 achieves high accuracy and low cost by using Enhanced dual bit DS techniques. The AK5384 supports master mode and TDM format. Therefore,

18 (16/30) AWG Tinned Copper

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In-System Programmable 3.3V SuperWIDE??High Density PLD

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24bit 96kHz 4ch A/D converter

文件：269.85 Kbytes Page：23 Pages