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ISPLSI5384VE-125LF256中文资料
ISPLSI5384VE-125LF256数据手册规格书PDF详情
ispLSI 5000VE Description
The ispLSI 5000VE Family of In-System Programmable High Density Logic Devices is based on Generic Logic Blocks (GLBs) of 32 registered macrocells and a single Global Routing Pool (GRP) structure interconnecting the GLBs.
Outputs from the GLBs drive the Global Routing Pool (GRP) between the GLBs. Switching resources are provided to allow signals in the Global Routing Pool to drive any or all the GLBs in the device. This mechanism allows fast, efficient connections across the entire device.
Features
• Second Generation SuperWIDE HIGH DENSITY IN-SYSTEM PROGRAMMABLE LOGIC DEVICE
— 3.3V Power Supply
— User Selectable 3.3V/2.5V I/O
— 18000 PLD Gates / 384 Macrocells
— Up to 192 I/O Pins
— 384 Registers
— High-Speed Global Interconnect
— SuperWIDE Generic Logic Block (32 Macrocells) for Optimum Performance
— SuperWIDE Input Gating (68 Inputs) for Fast Counters, State Machines, Address Decoders, etc.
— PCB Efficient Ball Grid Array (BGA) Package Options
— Interfaces with Standard 5V TTL Devices
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY
— fmax = 165 MHz Maximum Operating Frequency
— tpd = 6.0 ns Propagation Delay
— TTL/3.3V/2.5V Compatible Input Thresholds and Output Levels
— Electrically Erasable and Reprogrammable
— Non-Volatile
— Programmable Speed/Power Logic Path Optimization
• IN-SYSTEM PROGRAMMABLE
— Increased Manufacturing Yields, Reduced Time-toMarket, and Improved Product Quality
— Reprogram Soldered Devices for Faster Debugging
• 100 IEEE 1149.1 BOUNDARY SCAN TESTABLE AND 3.3V IN-SYSTEM PROGRAMMABLE
• ARCHITECTURE FEATURES
— Enhanced Pin-Locking Architecture with SingleLevel Global Routing Pool and SuperWIDE GLBs
— Wrap Around Product Term Sharing Array Supports up to 35 Product Terms Per Macrocell
— Macrocells Support Concurrent Combinatorial and Registered Functions
— Macrocell Registers Feature Multiple Control Options Including Set, Reset and Clock Enable
— Four Dedicated Clock Input Pins Plus Macrocell Product Term Clocks
— Programmable I/O Supports Programmable Bus Hold, Pull-up, Open Drain and Slew Rate Options
— Four Global Product Term Output Enables, Two Global OE Pins and One Product Term OE per Macrocell
ISPLSI5384VE-125LF256产品属性
- 类型
描述
- 型号
ISPLSI5384VE-125LF256
- 功能描述
CPLD - 复杂可编程逻辑器件
- RoHS
否
- 制造商
Lattice
- 存储类型
EEPROM
- 大电池数量
128
- 最大工作频率
333 MHz
- 延迟时间
2.7 ns
- 可编程输入/输出端数量
64
- 工作电源电压
3.3 V
- 最大工作温度
+ 90 C
- 最小工作温度
0 C
- 封装/箱体
TQFP-100
供应商 | 型号 | 品牌 | 批号 | 封装 | 库存 | 备注 | 价格 |
---|---|---|---|---|---|---|---|
LATTICE |
24+ |
BGA |
23000 |
免费送样原盒原包现货一手渠道联系 |
|||
LATTICE |
2025+ |
BGA |
4119 |
全新原装、公司现货热卖 |
|||
LATTICE |
21+ |
BGA |
10000 |
原装现货假一罚十 |
|||
LATTICE |
1101+ |
BGA |
38 |
一级代理,专注军工、汽车、医疗、工业、新能源、电力 |
|||
LATTICE |
23+ |
BGA |
28000 |
原装正品 |
|||
LATTICE |
20+ |
BGA-256 |
1001 |
就找我吧!--邀您体验愉快问购元件! |
|||
LATTICE |
23+ |
BGA |
12800 |
##公司主营品牌长期供应100%原装现货可含税提供技术 |
|||
LATTICE |
23+ |
BGA |
8560 |
受权代理!全新原装现货特价热卖! |
|||
LATTICE |
23+ |
BGA |
8000 |
只做原装现货 |
|||
Lattice |
2318+ |
BGA-256 |
4980 |
Lattice全系列进口原装特价 |
ISPLSI5384VE-125LF256 资料下载更多...
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