位置：首页 > IC中文资料第1061页 > ISPLSI5256VE
| 型号 | 功能描述 | 生产厂家 企业 | LOGO | 操作 |
|---|---|---|---|---|
ISPLSI5256VE | In-System Programmable 3.3V SuperWIDE High Density PLD ispLSI 5000VE Description The ispLSI 5000VE Family of In-System Programmable High Density Logic Devices is based on Generic Logic Blocks (GLBs) of 32 registered macrocells and a single Global Routing Pool (GRP) structure interconnecting the GLBs. Outputs from the GLBs drive the Global Routin | Lattice 莱迪思 |   | |
ISPLSI5256VE | In-System Programmable 3.3V SuperWIDE™ High Density PLD Features • Second Generation SuperWIDE HIGH DENSITY IN-SYSTEM PROGRAMMABLE LOGIC DEVICE — 3.3V Power Supply — User Selectable 3.3V/2.5V I/O — 24000 PLD Gates / 512 Macrocells — Up to 256 I/O Pins — 512 Registers — High-Speed Global Interconnect — SuperWIDE Generic Logic Block (32 Macrocel | Lattice 莱迪思 | | |
ISPLSI5256VE | In-System Programmable 3.3V SuperWIDE™ High Density PLD | Lattice 莱迪思 | | |
In-System Programmable 3.3V SuperWIDE High Density PLD ispLSI 5000VE Description The ispLSI 5000VE Family of In-System Programmable High Density Logic Devices is based on Generic Logic Blocks (GLBs) of 32 registered macrocells and a single Global Routing Pool (GRP) structure interconnecting the GLBs. Outputs from the GLBs drive the Global Routin | Lattice 莱迪思 | | ||
In-System Programmable 3.3V SuperWIDE High Density PLD ispLSI 5000VE Description The ispLSI 5000VE Family of In-System Programmable High Density Logic Devices is based on Generic Logic Blocks (GLBs) of 32 registered macrocells and a single Global Routing Pool (GRP) structure interconnecting the GLBs. Outputs from the GLBs drive the Global Routin | Lattice 莱迪思 | | ||
In-System Programmable 3.3V SuperWIDE High Density PLD ispLSI 5000VE Description The ispLSI 5000VE Family of In-System Programmable High Density Logic Devices is based on Generic Logic Blocks (GLBs) of 32 registered macrocells and a single Global Routing Pool (GRP) structure interconnecting the GLBs. Outputs from the GLBs drive the Global Routin | Lattice 莱迪思 | | ||
In-System Programmable 3.3V SuperWIDE High Density PLD ispLSI 5000VE Description The ispLSI 5000VE Family of In-System Programmable High Density Logic Devices is based on Generic Logic Blocks (GLBs) of 32 registered macrocells and a single Global Routing Pool (GRP) structure interconnecting the GLBs. Outputs from the GLBs drive the Global Routin | Lattice 莱迪思 | | ||
In-System Programmable 3.3V SuperWIDE High Density PLD ispLSI 5000VE Description The ispLSI 5000VE Family of In-System Programmable High Density Logic Devices is based on Generic Logic Blocks (GLBs) of 32 registered macrocells and a single Global Routing Pool (GRP) structure interconnecting the GLBs. Outputs from the GLBs drive the Global Routin | Lattice 莱迪思 | | ||
In-System Programmable 3.3V SuperWIDE High Density PLD ispLSI 5000VE Description The ispLSI 5000VE Family of In-System Programmable High Density Logic Devices is based on Generic Logic Blocks (GLBs) of 32 registered macrocells and a single Global Routing Pool (GRP) structure interconnecting the GLBs. Outputs from the GLBs drive the Global Routin | Lattice 莱迪思 | | ||
In-System Programmable 3.3V SuperWIDE High Density PLD ispLSI 5000VE Description The ispLSI 5000VE Family of In-System Programmable High Density Logic Devices is based on Generic Logic Blocks (GLBs) of 32 registered macrocells and a single Global Routing Pool (GRP) structure interconnecting the GLBs. Outputs from the GLBs drive the Global Routin | Lattice 莱迪思 | | ||
In-System Programmable 3.3V SuperWIDE High Density PLD ispLSI 5000VE Description The ispLSI 5000VE Family of In-System Programmable High Density Logic Devices is based on Generic Logic Blocks (GLBs) of 32 registered macrocells and a single Global Routing Pool (GRP) structure interconnecting the GLBs. Outputs from the GLBs drive the Global Routin | Lattice 莱迪思 | | ||
In-System Programmable 3.3V SuperWIDE High Density PLD ispLSI 5000VE Description The ispLSI 5000VE Family of In-System Programmable High Density Logic Devices is based on Generic Logic Blocks (GLBs) of 32 registered macrocells and a single Global Routing Pool (GRP) structure interconnecting the GLBs. Outputs from the GLBs drive the Global Routin | Lattice 莱迪思 | | ||
In-System Programmable 3.3V SuperWIDE High Density PLD ispLSI 5000VE Description The ispLSI 5000VE Family of In-System Programmable High Density Logic Devices is based on Generic Logic Blocks (GLBs) of 32 registered macrocells and a single Global Routing Pool (GRP) structure interconnecting the GLBs. Outputs from the GLBs drive the Global Routin | Lattice 莱迪思 | | ||
In-System Programmable 3.3V SuperWIDE High Density PLD ispLSI 5000VE Description The ispLSI 5000VE Family of In-System Programmable High Density Logic Devices is based on Generic Logic Blocks (GLBs) of 32 registered macrocells and a single Global Routing Pool (GRP) structure interconnecting the GLBs. Outputs from the GLBs drive the Global Routin | Lattice 莱迪思 | | ||
In-System Programmable 3.3V SuperWIDE High Density PLD ispLSI 5000VE Description The ispLSI 5000VE Family of In-System Programmable High Density Logic Devices is based on Generic Logic Blocks (GLBs) of 32 registered macrocells and a single Global Routing Pool (GRP) structure interconnecting the GLBs. Outputs from the GLBs drive the Global Routin | Lattice 莱迪思 | | ||
In-System Programmable 3.3V SuperWIDE High Density PLD ispLSI 5000VE Description The ispLSI 5000VE Family of In-System Programmable High Density Logic Devices is based on Generic Logic Blocks (GLBs) of 32 registered macrocells and a single Global Routing Pool (GRP) structure interconnecting the GLBs. Outputs from the GLBs drive the Global Routin | Lattice 莱迪思 | | ||
In-System Programmable 3.3V SuperWIDE High Density PLD ispLSI 5000VE Description The ispLSI 5000VE Family of In-System Programmable High Density Logic Devices is based on Generic Logic Blocks (GLBs) of 32 registered macrocells and a single Global Routing Pool (GRP) structure interconnecting the GLBs. Outputs from the GLBs drive the Global Routin | Lattice 莱迪思 | | ||
In-System Programmable 3.3V SuperWIDE High Density PLD ispLSI 5000VE Description The ispLSI 5000VE Family of In-System Programmable High Density Logic Devices is based on Generic Logic Blocks (GLBs) of 32 registered macrocells and a single Global Routing Pool (GRP) structure interconnecting the GLBs. Outputs from the GLBs drive the Global Routin | Lattice 莱迪思 | | ||
In-System Programmable 3.3V SuperWIDE High Density PLD ispLSI 5000VE Description The ispLSI 5000VE Family of In-System Programmable High Density Logic Devices is based on Generic Logic Blocks (GLBs) of 32 registered macrocells and a single Global Routing Pool (GRP) structure interconnecting the GLBs. Outputs from the GLBs drive the Global Routin | Lattice 莱迪思 | | ||
In-System Programmable 3.3V SuperWIDE High Density PLD ispLSI 5000VE Description The ispLSI 5000VE Family of In-System Programmable High Density Logic Devices is based on Generic Logic Blocks (GLBs) of 32 registered macrocells and a single Global Routing Pool (GRP) structure interconnecting the GLBs. Outputs from the GLBs drive the Global Routin | Lattice 莱迪思 | | ||
In-System Programmable 3.3V SuperWIDE High Density PLD ispLSI 5000VE Description The ispLSI 5000VE Family of In-System Programmable High Density Logic Devices is based on Generic Logic Blocks (GLBs) of 32 registered macrocells and a single Global Routing Pool (GRP) structure interconnecting the GLBs. Outputs from the GLBs drive the Global Routin | Lattice 莱迪思 | | ||
In-System Programmable 3.3V SuperWIDE High Density PLD ispLSI 5000VE Description The ispLSI 5000VE Family of In-System Programmable High Density Logic Devices is based on Generic Logic Blocks (GLBs) of 32 registered macrocells and a single Global Routing Pool (GRP) structure interconnecting the GLBs. Outputs from the GLBs drive the Global Routin | Lattice 莱迪思 | | ||
In-System Programmable 3.3V SuperWIDE High Density PLD ispLSI 5000VE Description The ispLSI 5000VE Family of In-System Programmable High Density Logic Devices is based on Generic Logic Blocks (GLBs) of 32 registered macrocells and a single Global Routing Pool (GRP) structure interconnecting the GLBs. Outputs from the GLBs drive the Global Routin | Lattice 莱迪思 | | ||
In-System Programmable 3.3V SuperWIDE High Density PLD ispLSI 5000VE Description The ispLSI 5000VE Family of In-System Programmable High Density Logic Devices is based on Generic Logic Blocks (GLBs) of 32 registered macrocells and a single Global Routing Pool (GRP) structure interconnecting the GLBs. Outputs from the GLBs drive the Global Routin | Lattice 莱迪思 | | ||
In-System Programmable 3.3V SuperWIDE High Density PLD ispLSI 5000VE Description The ispLSI 5000VE Family of In-System Programmable High Density Logic Devices is based on Generic Logic Blocks (GLBs) of 32 registered macrocells and a single Global Routing Pool (GRP) structure interconnecting the GLBs. Outputs from the GLBs drive the Global Routin | Lattice 莱迪思 | | ||
In-System Programmable 3.3V SuperWIDE High Density PLD ispLSI 5000VE Description The ispLSI 5000VE Family of In-System Programmable High Density Logic Devices is based on Generic Logic Blocks (GLBs) of 32 registered macrocells and a single Global Routing Pool (GRP) structure interconnecting the GLBs. Outputs from the GLBs drive the Global Routin | Lattice 莱迪思 | | ||
In-System Programmable 3.3V SuperWIDE High Density PLD ispLSI 5000VE Description The ispLSI 5000VE Family of In-System Programmable High Density Logic Devices is based on Generic Logic Blocks (GLBs) of 32 registered macrocells and a single Global Routing Pool (GRP) structure interconnecting the GLBs. Outputs from the GLBs drive the Global Routin | Lattice 莱迪思 | | ||
Hash Choke 文件：2.31952 Mbytes Page：2 Pages | Bourns 伯恩斯 | | ||
5200 Series - Hash Choke 文件：2.28613 Mbytes Page：2 Pages | Bourns 伯恩斯 | | ||
5200 Series - Hash Choke 文件：2.31952 Mbytes Page：2 Pages | Bourns 伯恩斯 | | ||
In-System Programmable 3.3V SuperWIDE??High Density PLD 文件：311.85 Kbytes Page：25 Pages | Lattice 莱迪思 | | ||
In-System Programmable 3.3V SuperWIDE??High Density PLD 文件：311.44 Kbytes Page：25 Pages | Lattice 莱迪思 | |
ISPLSI5256VE产品属性
- 类型
描述
- 型号
ISPLSI5256VE
- 功能描述
CPLD - 复杂可编程逻辑器件
- RoHS
否
- 制造商
Lattice
- 存储类型
EEPROM
- 大电池数量
128
- 最大工作频率
333 MHz
- 延迟时间
2.7 ns
- 可编程输入/输出端数量
64
- 工作电源电压
3.3 V
- 最大工作温度
+ 90 C
- 最小工作温度
0 C
- 封装/箱体
TQFP-100
| IC供应商 | 芯片型号 | 品牌 | 批号 | 封装 | 库存 | 备注 | 价格 |
|---|---|---|---|---|---|---|---|
LATTICE |
24+ |
NA |
2000 |
只做原装正品现货 欢迎来电查询15919825718 |
|||
LATTICE |
24+ |
FPBGA256 |
7850 |
只做原装正品现货或订货假一赔十! |
|||
PERCICOM |
2025+ |
BGA |
4119 |
全新原装、公司现货热卖 |
|||
LATTICE |
原厂封装 |
9800 |
原装进口公司现货假一赔百 |
||||
LATTICE |
24+ |
QFP |
6980 |
原装现货,可开13%税票 |
|||
LATTICE |
NEW |
FPBGA256 |
19726 |
代理全系列销售,全新原装正品,价格优势,长期供应,量大可订 |
|||
LATTICE |
25+23+ |
BGA |
13397 |
绝对原装正品全新进口深圳现货 |
|||
LATTICE |
NA |
5650 |
一级代理 原装正品假一罚十价格优势长期供货 |
||||
LATTACE |
20+ |
LQFP |
2860 |
原厂原装正品价格优惠公司现货欢迎查询 |
|||
LATTICE |
25+ |
TQFP128 |
3000 |
全新原装、诚信经营、公司现货销售 |
ISPLSI5256VE芯片相关品牌
ISPLSI5256VE规格书下载地址
ISPLSI5256VE参数引脚图相关
- l234
- l101
- l100
- ku波段
- kt250
- kse13005
- ks20
- km710
- ka5q1265rf
- k9f1208
- k310
- k2698
- k233
- k2055
- k2010
- jumper
- jtag接口
- jk触发器
- j111
- j108
- ISTS300
- ISTS250
- ISTS200
- ISTS150
- ISTS149
- ISTS100
- IS-T-F
- IST3028
- ISS-8
- ISS-6
- ISRL860
- ISR860
- ISR820
- ISQ74X
- ISQ74
- ISQ204
- ISQ203
- ISQ202
- ISQ201
- ISPXPGA
- ISPLSI5256VE-165LT128
- ISPLSI5256VE-165LT100
- ISPLSI5256VE-165LF256
- ISPLSI5256VE-165LB272
- ISPLSI5256VE-125LT128I
- ISPLSI5256VE-125LT128
- ISPLSI5256VE-125LT100I
- ISPLSI5256VE-125LT100
- ISPLSI5256VE-125LF256I
- ISPLSI5256VE-125LF256
- ISPLSI5256VE-125LB272I
- ISPLSI5256VE-125LB272
- ISPLSI5256VE-100LT128I
- ISPLSI5256VE-100LT128
- ISPLSI5256VE-100LT100I
- ISPLSI5256VE-100LT100
- ISPLSI5256VE-100LF256I
- ISPLSI5256VE-100LF256
- ISPLSI5256VE-100LB272I
- ISPLSI5256VE-100LB272
- ISPLSI5256VA-70LQ208
- ISPLSI5256VA-70LB272I
- ISPLSI5256VA-70LB272
- ISPLSI5256VA-70LB208
- ISPLSI5256VA-125LQ208
- ISPLSI5256VA125LQ208
- ISPLSI5256VA-125LB272
- ISPLSI5256VA-125LB208
- ISPLSI5256VA-100LQ208
- ISPLSI5256VA-100LB272
- ISPLSI5256VA-100LB208I
- ISPLSI5256VA-100LB208
- ISPLSI5128VE-80LT128I
- ISPLSI5128VE-180LTN128
- ISPLSI5128VE-180LT128
- ISPLSI5128VE-125LT128I
- ISPLSI5128VE-125LT128
- ISPLSI5128VE-100LT128I
- ISPLSI5128VE-100LT128
- ISPLSI-3448-90LB432
- ISPICR1
- ISPGDX2
- ISPGDX
- ISPD65
- ISPD64
- ISPD63
- ISPD62
- ISPD61
- ISPD60
- ISPB40
- ISPB35
- ISPB20
- ISPA60
- ISPA40
- ISPA20
- ISPA06
- ISP847X
- ISP847
- ISP845X
- ISP845
ISPLSI5256VE数据表相关新闻
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2019-7-22ISPLSI2096V-80LT128
ISPLSI2096V-80LT128 本公司具备一般纳税人，可开13点增值税票， 货源渠道保证原厂原装正品IC，诚信为本，薄利多销。
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ISPLSI2096V-80LQ128 本公司具备一般纳税人，可开13点增值税票， 货源渠道保证原厂原装正品IC，诚信为本，薄利多销。
2019-5-7IT6515FN/BX-0051绝对原装正品公司现货
瀚佳科技： 专业销售集成电路IC.单片.内存闪存.二三级管模块等电子元器件.欢迎询价购买。
2018-12-28
DdatasheetPDF页码索引
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