Adjustable Quad Sequencer

The ISL8700A, ISL8701A, ISL8702A, ISL8703A, ISL8704A, ISL8705A family of ICs provide four delay adjustable sequenced outputs while monitoring an input voltage all with a minimum of external components. High performance DSP, FPGA, µP and various sub-systems require input power sequencing for p

封装/外壳：14-SOIC（0.154"，3.90mm 宽） 包装：管件 描述：IC SUPERVISOR 4 CHANNEL 14SOIC 集成电路（IC） 监控器

Adjustable Delay to Subsequent Enable Signal

文件：607.12 Kbytes Page：12 Pages

Adjustable Quad Sequencer

文件：289.82 Kbytes Page：12 Pages

封装/外壳：14-SOIC（0.154"，3.90mm 宽） 包装：卷带（TR） 描述：IC SUPERVISOR 4 CHANNEL 14SOIC 集成电路（IC） 监控器

Zero Delay, Differential-to-LVCMOS/ LVTTL Clock Generator

FEATURES • Eight LVCMOS/LVTTL outputs, 7Ω typical output impedance • Selectable CLK1, nCLK1 or LVCMOS/LVTTL clock inputs • CLK1, nCLK1 pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL • CLK0 input accepts LVCMOS or LVTTL input levels • Output frequenc

Zero Delay, Differential-to-LVCMOS/ LVTTL Clock Generator

FEATURES • Eight LVCMOS/LVTTL outputs, 7Ω typical output impedance • Selectable CLK1, nCLK1 or LVCMOS/LVTTL clock inputs • CLK1, nCLK1 pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL • CLK0 input accepts LVCMOS or LVTTL input levels • Output frequenc

CAPTIVE PANEL SCREWS

文件：395.93 Kbytes Page：1 Pages

ZERO DELAY, DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR

文件：183.45 Kbytes Page：18 Pages

ZERO DELAY, DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR

文件：183.45 Kbytes Page：18 Pages