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IS64L价格
参考价格：￥64.1787
型号：IS64LF12832A-7.5TQLA3 品牌：ISSI 备注：这里有IS64L多少钱，2025年最近7天走势，今日出价，今日竞价，IS64L批发/采购报价，IS64L行情走势销售排行榜，IS64L报价。| 型号 | 功能描述 | 生产厂家 企业 | LOGO | 操作 |
|---|---|---|---|---|
128K x 32, 128K x 36, 256K x 18 4 Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM DESCRIPTION The ISSI IS61(64)LF12832A, IS64VF12832A, IS61(64)LF/VF12836A and IS61(64)LF/VF25618A are high-speed, low-power synchronous static RAMs designed to provide burstable, high-performance memory for communication and networking applications. The IS61(64)LF12832A is organized as 131,072 wor | ISSI 矽成半导体 |   | ||
128K x 32, 128K x 36, 256K x 18 4 Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM DESCRIPTION The ISSI IS61(64)LF12832A, IS64VF12832A, IS61(64)LF/VF12836A and IS61(64)LF/VF25618A are high-speed, low-power synchronous static RAMs designed to provide burstable, high-performance memory for communication and networking applications. The IS61(64)LF12832A is organized as 131,072 wor | ISSI 矽成半导体 | | ||
128K x 32, 128K x 36, 256K x 18 4 Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM DESCRIPTION The ISSI IS61(64)LF12832A, IS64VF12832A, IS61(64)LF/VF12836A and IS61(64)LF/VF25618A are high-speed, low-power synchronous static RAMs designed to provide burstable, high-performance memory for communication and networking applications. The IS61(64)LF12832A is organized as 131,072 wor | ISSI 矽成半导体 | | ||
128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS FLOW-THROUGH SRAM FEATURES Internal self-timed write cycle Individual Byte Write Control and Global Write Clock controlled, registered address, data and control Burst sequence control using MODE input Three chip enable option for simple depth expansion and address pipelining Common data inputs an | ISSI 矽成半导体 | | ||
128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS FLOW-THROUGH SRAM FEATURES Internal self-timed write cycle Individual Byte Write Control and Global Write Clock controlled, registered address, data and control Burst sequence control using MODE input Three chip enable option for simple depth expansion and address pipelining Common data inputs an | ISSI 矽成半导体 | | ||
128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS FLOW-THROUGH SRAM FEATURES Internal self-timed write cycle Individual Byte Write Control and Global Write Clock controlled, registered address, data and control Burst sequence control using MODE input Three chip enable option for simple depth expansion and address pipelining Common data inputs an | ISSI 矽成半导体 | | ||
128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS FLOW-THROUGH SRAM FEATURES Internal self-timed write cycle Individual Byte Write Control and Global Write Clock controlled, registered address, data and control Burst sequence control using MODE input Three chip enable option for simple depth expansion and address pipelining Common data inputs an | ISSI 矽成半导体 | | ||
128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS FLOW-THROUGH SRAM FEATURES Internal self-timed write cycle Individual Byte Write Control and Global Write Clock controlled, registered address, data and control Burst sequence control using MODE input Three chip enable option for simple depth expansion and address pipelining Common data inputs an | ISSI 矽成半导体 | | ||
128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS FLOW-THROUGH SRAM FEATURES Internal self-timed write cycle Individual Byte Write Control and Global Write Clock controlled, registered address, data and control Burst sequence control using MODE input Three chip enable option for simple depth expansion and address pipelining Common data inputs an | ISSI 矽成半导体 | | ||
128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS FLOW-THROUGH SRAM FEATURES Internal self-timed write cycle Individual Byte Write Control and Global Write Clock controlled, registered address, data and control Burst sequence control using MODE input Three chip enable option for simple depth expansion and address pipelining Common data inputs an | ISSI 矽成半导体 | | ||
128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS FLOW-THROUGH SRAM FEATURES Internal self-timed write cycle Individual Byte Write Control and Global Write Clock controlled, registered address, data and control Burst sequence control using MODE input Three chip enable option for simple depth expansion and address pipelining Common data inputs an | ISSI 矽成半导体 | | ||
128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS FLOW-THROUGH SRAM FEATURES Internal self-timed write cycle Individual Byte Write Control and Global Write Clock controlled, registered address, data and control Burst sequence control using MODE input Three chip enable option for simple depth expansion and address pipelining Common data inputs an | ISSI 矽成半导体 | | ||
128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS FLOW-THROUGH SRAM FEATURES Internal self-timed write cycle Individual Byte Write Control and Global Write Clock controlled, registered address, data and control Burst sequence control using MODE input Three chip enable option for simple depth expansion and address pipelining Common data inputs an | ISSI 矽成半导体 | | ||
128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS FLOW-THROUGH SRAM FEATURES Internal self-timed write cycle Individual Byte Write Control and Global Write Clock controlled, registered address, data and control Burst sequence control using MODE input Three chip enable option for simple depth expansion and address pipelining Common data inputs an | ISSI 矽成半导体 | | ||
128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS FLOW-THROUGH SRAM FEATURES Internal self-timed write cycle Individual Byte Write Control and Global Write Clock controlled, registered address, data and control Burst sequence control using MODE input Three chip enable option for simple depth expansion and address pipelining Common data inputs an | ISSI 矽成半导体 | | ||
128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS FLOW-THROUGH SRAM FEATURES Internal self-timed write cycle Individual Byte Write Control and Global Write Clock controlled, registered address, data and control Burst sequence control using MODE input Three chip enable option for simple depth expansion and address pipelining Common data inputs an | ISSI 矽成半导体 | | ||
128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS FLOW-THROUGH SRAM FEATURES Internal self-timed write cycle Individual Byte Write Control and Global Write Clock controlled, registered address, data and control Burst sequence control using MODE input Three chip enable option for simple depth expansion and address pipelining Common data inputs an | ISSI 矽成半导体 | | ||
128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS FLOW-THROUGH SRAM FEATURES Internal self-timed write cycle Individual Byte Write Control and Global Write Clock controlled, registered address, data and control Burst sequence control using MODE input Three chip enable option for simple depth expansion and address pipelining Common data inputs an | ISSI 矽成半导体 | | ||
128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS FLOW-THROUGH SRAM FEATURES Internal self-timed write cycle Individual Byte Write Control and Global Write Clock controlled, registered address, data and control Burst sequence control using MODE input Three chip enable option for simple depth expansion and address pipelining Common data inputs an | ISSI 矽成半导体 | | ||
128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS FLOW-THROUGH SRAM FEATURES Internal self-timed write cycle Individual Byte Write Control and Global Write Clock controlled, registered address, data and control Burst sequence control using MODE input Three chip enable option for simple depth expansion and address pipelining Common data inputs an | ISSI 矽成半导体 | | ||
128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS FLOW-THROUGH SRAM FEATURES Internal self-timed write cycle Individual Byte Write Control and Global Write Clock controlled, registered address, data and control Burst sequence control using MODE input Three chip enable option for simple depth expansion and address pipelining Common data inputs an | ISSI 矽成半导体 | | ||
128K x 32, 128K x 36, 256K x 18 4 Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM DESCRIPTION The ISSI IS61(64)LF12832A, IS64VF12832A, IS61(64)LF/VF12836A and IS61(64)LF/VF25618A are high-speed, low-power synchronous static RAMs designed to provide burstable, high-performance memory for communication and networking applications. The IS61(64)LF12832A is organized as 131,072 wor | ISSI 矽成半导体 | | ||
128K x 32, 128K x 36, 256K x 18 4 Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM DESCRIPTION The ISSI IS61(64)LF12832A, IS64VF12832A, IS61(64)LF/VF12836A and IS61(64)LF/VF25618A are high-speed, low-power synchronous static RAMs designed to provide burstable, high-performance memory for communication and networking applications. The IS61(64)LF12832A is organized as 131,072 wor | ISSI 矽成半导体 | | ||
128K x 32, 128K x 36, 256K x 18 4 Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM DESCRIPTION The ISSI IS61(64)LF12832A, IS64VF12832A, IS61(64)LF/VF12836A and IS61(64)LF/VF25618A are high-speed, low-power synchronous static RAMs designed to provide burstable, high-performance memory for communication and networking applications. The IS61(64)LF12832A is organized as 131,072 wor | ISSI 矽成半导体 | | ||
128K x 32, 128K x 36, 256K x 18 4 Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM DESCRIPTION The ISSI IS61(64)LF12832A, IS64VF12832A, IS61(64)LF/VF12836A and IS61(64)LF/VF25618A are high-speed, low-power synchronous static RAMs designed to provide burstable, high-performance memory for communication and networking applications. The IS61(64)LF12832A is organized as 131,072 wor | ISSI 矽成半导体 | | ||
256K x 36, 512K x 18 9 Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs a | ISSI 矽成半导体 | | ||
256K x 36, 512K x 18 9 Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs a | ISSI 矽成半导体 | | ||
256K x 36, 512K x 18 9 Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs a | ISSI 矽成半导体 | | ||
256K x 36, 512K x 18 9 Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs a | ISSI 矽成半导体 | | ||
512K x36 and 1024K x18 18Mb, SYNCHRONOUS FLOW-THROUGH SRAM FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs an | ISSI 矽成半导体 | | ||
512K x36 and 1024K x18 18Mb, SYNCHRONOUS FLOW-THROUGH SRAM FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs an | ISSI 矽成半导体 | | ||
512K x36 and 1024K x18 18Mb, SYNCHRONOUS FLOW-THROUGH SRAM FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs an | ISSI 矽成半导体 | | ||
1M x 36, 1M x 32, 2M x 18 36 Mb SYNCHRONOUS PIPELINED, Single CYCLE DESELECT STATIC RAM FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs a | ISSI 矽成半导体 | | ||
1M x 36, 1M x 32, 2M x 18 36 Mb SYNCHRONOUS PIPELINED, Single CYCLE DESELECT STATIC RAM FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs a | ISSI 矽成半导体 | | ||
1M x 36, 1M x 32, 2M x 18 36 Mb SYNCHRONOUS PIPELINED, Single CYCLE DESELECT STATIC RAM FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs a | ISSI 矽成半导体 | | ||
1M x 36, 1M x 32, 2M x 18 36 Mb SYNCHRONOUS PIPELINED, Single CYCLE DESELECT STATIC RAM FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs a | ISSI 矽成半导体 | | ||
1M x 36, 1M x 32, 2M x 18 36 Mb SYNCHRONOUS PIPELINED, Single CYCLE DESELECT STATIC RAM FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs a | ISSI 矽成半导体 | | ||
1M x 36, 1M x 32, 2M x 18 36 Mb SYNCHRONOUS PIPELINED, Single CYCLE DESELECT STATIC RAM FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs a | ISSI 矽成半导体 | | ||
128K x 32, 128K x 36, 256K x 18 4 Mb SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT STATIC RAM DESCRIPTION The ISSIIS61(64)LPS12832A, IS61(64)LPS/VPS12836A and IS61(64)LPS/VPS25618A are high-speed, low-power synchronous static RAMs designed to provide burstable, high-performancememory for communication and networking applications. The IS61(64)LPS12832A is organized as 131,072 words by 32 b | ISSI 矽成半导体 | | ||
128K x 32, 128K x 36, 256K x 18 4 Mb SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT STATIC RAM DESCRIPTION The ISSIIS61(64)LPS12832A, IS61(64)LPS/VPS12836A and IS61(64)LPS/VPS25618A are high-speed, low-power synchronous static RAMs designed to provide burstable, high-performancememory for communication and networking applications. The IS61(64)LPS12832A is organized as 131,072 words by 32 b | ISSI 矽成半导体 | | ||
128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT SRAM FEATURES Internal self-timed write cycle Individual Byte Write Control and Global Write Clock controlled, registered address, data and control Burst sequence control using MODE input Three chip enable option for simple depth expansion and address pipelining Common data inputs an | ISSI 矽成半导体 | | ||
128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT SRAM FEATURES Internal self-timed write cycle Individual Byte Write Control and Global Write Clock controlled, registered address, data and control Burst sequence control using MODE input Three chip enable option for simple depth expansion and address pipelining Common data inputs an | ISSI 矽成半导体 | | ||
128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT SRAM FEATURES Internal self-timed write cycle Individual Byte Write Control and Global Write Clock controlled, registered address, data and control Burst sequence control using MODE input Three chip enable option for simple depth expansion and address pipelining Common data inputs an | ISSI 矽成半导体 | | ||
128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT SRAM FEATURES Internal self-timed write cycle Individual Byte Write Control and Global Write Clock controlled, registered address, data and control Burst sequence control using MODE input Three chip enable option for simple depth expansion and address pipelining Common data inputs an | ISSI 矽成半导体 | | ||
128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT SRAM FEATURES Internal self-timed write cycle Individual Byte Write Control and Global Write Clock controlled, registered address, data and control Burst sequence control using MODE input Three chip enable option for simple depth expansion and address pipelining Common data inputs an | ISSI 矽成半导体 | | ||
128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT SRAM FEATURES Internal self-timed write cycle Individual Byte Write Control and Global Write Clock controlled, registered address, data and control Burst sequence control using MODE input Three chip enable option for simple depth expansion and address pipelining Common data inputs an | ISSI 矽成半导体 | | ||
128K x 32, 128K x 36, 256K x 18 4 Mb SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT STATIC RAM DESCRIPTION The ISSIIS61(64)LPS12832A, IS61(64)LPS/VPS12836A and IS61(64)LPS/VPS25618A are high-speed, low-power synchronous static RAMs designed to provide burstable, high-performancememory for communication and networking applications. The IS61(64)LPS12832A is organized as 131,072 words by 32 b | ISSI 矽成半导体 | | ||
128K x 32, 128K x 36, 256K x 18 4 Mb SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT STATIC RAM DESCRIPTION The ISSIIS61(64)LPS12832A, IS61(64)LPS/VPS12836A and IS61(64)LPS/VPS25618A are high-speed, low-power synchronous static RAMs designed to provide burstable, high-performancememory for communication and networking applications. The IS61(64)LPS12832A is organized as 131,072 words by 32 b | ISSI 矽成半导体 | | ||
128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT SRAM FEATURES Internal self-timed write cycle Individual Byte Write Control and Global Write Clock controlled, registered address, data and control Burst sequence control using MODE input Three chip enable option for simple depth expansion and address pipelining Common data inputs an | ISSI 矽成半导体 | | ||
128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT SRAM FEATURES Internal self-timed write cycle Individual Byte Write Control and Global Write Clock controlled, registered address, data and control Burst sequence control using MODE input Three chip enable option for simple depth expansion and address pipelining Common data inputs an | ISSI 矽成半导体 | | ||
128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT SRAM FEATURES Internal self-timed write cycle Individual Byte Write Control and Global Write Clock controlled, registered address, data and control Burst sequence control using MODE input Three chip enable option for simple depth expansion and address pipelining Common data inputs an | ISSI 矽成半导体 | | ||
128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT SRAM FEATURES Internal self-timed write cycle Individual Byte Write Control and Global Write Clock controlled, registered address, data and control Burst sequence control using MODE input Three chip enable option for simple depth expansion and address pipelining Common data inputs an | ISSI 矽成半导体 | | ||
128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT SRAM FEATURES Internal self-timed write cycle Individual Byte Write Control and Global Write Clock controlled, registered address, data and control Burst sequence control using MODE input Three chip enable option for simple depth expansion and address pipelining Common data inputs an | ISSI 矽成半导体 | | ||
128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT SRAM FEATURES Internal self-timed write cycle Individual Byte Write Control and Global Write Clock controlled, registered address, data and control Burst sequence control using MODE input Three chip enable option for simple depth expansion and address pipelining Common data inputs an | ISSI 矽成半导体 | | ||
128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT SRAM FEATURES Internal self-timed write cycle Individual Byte Write Control and Global Write Clock controlled, registered address, data and control Burst sequence control using MODE input Three chip enable option for simple depth expansion and address pipelining Common data inputs an | ISSI 矽成半导体 | | ||
128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT SRAM FEATURES Internal self-timed write cycle Individual Byte Write Control and Global Write Clock controlled, registered address, data and control Burst sequence control using MODE input Three chip enable option for simple depth expansion and address pipelining Common data inputs an | ISSI 矽成半导体 | | ||
128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT SRAM FEATURES Internal self-timed write cycle Individual Byte Write Control and Global Write Clock controlled, registered address, data and control Burst sequence control using MODE input Three chip enable option for simple depth expansion and address pipelining Common data inputs an | ISSI 矽成半导体 | | ||
128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT SRAM FEATURES Internal self-timed write cycle Individual Byte Write Control and Global Write Clock controlled, registered address, data and control Burst sequence control using MODE input Three chip enable option for simple depth expansion and address pipelining Common data inputs an | ISSI 矽成半导体 | | ||
128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT SRAM FEATURES Internal self-timed write cycle Individual Byte Write Control and Global Write Clock controlled, registered address, data and control Burst sequence control using MODE input Three chip enable option for simple depth expansion and address pipelining Common data inputs an | ISSI 矽成半导体 | | ||
128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT SRAM FEATURES Internal self-timed write cycle Individual Byte Write Control and Global Write Clock controlled, registered address, data and control Burst sequence control using MODE input Three chip enable option for simple depth expansion and address pipelining Common data inputs an | ISSI 矽成半导体 | |
IS64L产品属性
- 类型
描述
- 型号
IS64L
- 制造商
IDEC Corporation
- 制造商
IDEC Corporation
- 功能描述
SENS.IND. 10-30VDC PNP NO
| IC供应商 | 芯片型号 | 品牌 | 批号 | 封装 | 库存 | 备注 | 价格 |
|---|---|---|---|---|---|---|---|
ISSI(美国芯成) |
24+ |
TQFP100(14x20) |
7350 |
现货供应,当天可交货!免费送样,原厂技术支持!!! |
|||
ISSI Integrated Silicon Soluti |
22+ |
100TQFP (14x20) |
9000 |
原厂渠道,现货配单 |
|||
ISSI |
23+ |
100-TQFP(14x20) |
1389 |
专业分销产品!原装正品!价格优势! |
|||
ISSI |
23+ |
TQFP100 |
10000 |
原厂授权一级代理,专业海外优势订货,价格优势、品种 |
|||
ISS |
2018+ |
QFP100 |
26976 |
代理原装现货/特价热卖! |
|||
ISSI |
25+ |
QFP |
3200 |
全新原装、诚信经营、公司现货销售 |
|||
ISSI, |
25+ |
25000 |
原厂原包 深圳现货 主打品牌 假一赔百 可开票! |
||||
ISSI(美国芯成) |
2021+ |
TQFP-100(14x20) |
499 |
||||
ISSI |
24+ |
SOP-8 |
9000 |
只做原装正品 有挂有货 假一赔十 |
|||
ISSI |
2025+ |
TQFP100 |
4825 |
全新原厂原装产品、公司现货销售 |
IS64L规格书下载地址
IS64L参数引脚图相关
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- IS63LV1024L-10JLI
- IS62WV6416DBLL-45TLI
- IS62WV6416BLL-55TLI
- IS62WV6416BLL-55BLI
- IS62WV6416BLL-45BI
- IS62WV5128DBLL-45T2LI
- IS62WV5128DBLL-45HLI
- IS62WV5128BLL-55TLI
- IS62WV5128BLL-55T2LI
- IS627
- IS623
- IS622
- IS621
- IS620
- IS61C67
- IS611X
- IS611
- IS610X
- IS610
- IS609
- IS608X
- IS608
- IS607X
- IS607
- IS6051
- IS604X
- IS604
- IS6030
- IS6015X
IS64L数据表相关新闻
IS63WV1024BLL-12TLI
IS63WV1024BLL-12TLI, TSOP, ISSI, 22+
2023-3-9IS64LV51216-12TLA3
进口代理
2022-8-15IS82C55AZ 原装现货
IS82C55AZ 可做含税，支持实单
2021-9-22IS63LV1024L-12JL进口原装深圳现货
进口原装，国产代理，海量库存，产品齐全，货源渠道百分百正品
2020-6-19IS62WV5128BLL-55TLI
IS62WV5128BLL-55TLI，全新原装当天发货或门市自取0755-82732291.
2019-3-18IS916EN
IS916EN 深圳市拓亿芯电子有限公司，本公司具备一般纳税人，可开16点增值税票， 货源渠道保证原厂原装正品IC，诚信为本，薄利多销。
2019-3-6
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